Patents by Inventor Seok-Jae Chung

Seok-Jae Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8426837
    Abstract: Provided is a resistive memory device and a method of manufacturing the resistive memory device that includes a bottom electrode, an insulating layer that is formed on the bottom electrode and has a hole that exposes the bottom electrode, a resistance layer and an intermediate layer which are formed in the hole, a switch structure formed on a surface of the intermediate layer, and an upper electrode formed on the switch structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-jae Lee, Young-soo Park, Jung-hyun Lee, Soon-won Hwang, Seok-jae Chung, Chang-soo Lee
  • Patent number: 7504266
    Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: March 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Mann Lee, Hyun-Jo Kim, Jeong-Hee Park, Tae-Wan Kim, I-Hun Song, Seok-Jae Chung
  • Publication number: 20080278989
    Abstract: Provided is a resistive memory device and a method of manufacturing the resistive memory device that includes a bottom electrode, an insulating layer that is formed on the bottom electrode and has a hole that exposes the bottom electrode, a resistance layer and an intermediate layer which are formed in the hole, a switch structure formed on a surface of the intermediate layer, and an upper electrode formed on the switch structure.
    Type: Application
    Filed: March 7, 2008
    Publication date: November 13, 2008
    Inventors: Myoung-jae Lee, Young-soo Park, Jung-hyun Lee, Soon-won Hwang, Seok-jae Chung, Chang-soo Lee
  • Publication number: 20080164238
    Abstract: A method of etching a metal oxide layer formed on a metal layer is provided. The method includes mounting a specimen having the metal oxide layer and a photoresist on the metal oxide layer in a reaction chamber, wherein the metal oxide layer is formed on the metal layer and a pattern is formed on the photoresist. Primary etching of the metal oxide layer exposed by the photoresist may be performed using Cl2 gas in an inductively coupled plasma method. Secondary etching of residues remaining on an etched region of the metal oxide layer may be performed using BCl3 gas in the inductively coupled plasma method.
    Type: Application
    Filed: December 4, 2007
    Publication date: July 10, 2008
    Inventors: Seok-jae Chung, Soon-won Hwang, Jung-hyun Lee, Yeon-hee Kim
  • Patent number: 7397099
    Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-won Hwang, I-hun Song, Geun-young Yeom, Seok-jae Chung
  • Publication number: 20080087635
    Abstract: An etching method of a nickel oxide layer and a method of manufacturing a storage node of a resistive memory including the nickel oxide layer are provided. The method of etching the nickel oxide layer includes forming a nickel oxide layer on a substrate, forming a mask pattern on a desired region of the nickel oxide layer, removing the nickel oxide layer around the mask pattern using plasma generated from a mixed etching gas having a desired ratio of a main gas and an additive gas and removing the mask pattern.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 17, 2008
    Inventors: Soon-won Hwang, Jung-hyun Lee, Seok-jae Chung
  • Publication number: 20070164338
    Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.
    Type: Application
    Filed: February 26, 2007
    Publication date: July 19, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Soon-won Hwang, I-hun Song, Geun-young Yeom, Seok-jae Chung
  • Patent number: 7220601
    Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: May 22, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-won Hwang, I-hun Song, Geun-young Yeom, Seok-jae Chung
  • Publication number: 20060132986
    Abstract: A magnetoresistance device using TiN as a capping layer and a method of fabricating the same. The fabrication of the magnetoresistance device may be simpler and the magentoresistance device may be more stable and/or more reliable.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 22, 2006
    Inventors: Soon-Won Hwang, Tae-Wan Kim, Seok-Jae Chung, Yong-Hwan Yoo, Jee-Won Chung
  • Patent number: 6952364
    Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: October 4, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Mann Lee, Hyun-Jo Kim, Jeong-Hee Park, Tae-Wan Kim, I-Hun Song, Seok-Jae Chung
  • Publication number: 20050207219
    Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.
    Type: Application
    Filed: June 1, 2005
    Publication date: September 22, 2005
    Inventors: Kyu-Mann Lee, Hyun-Jo Kim, Jeong-Hee Park, Tae-Wan Kim, I-Hun Song, Seok-Jae Chung
  • Publication number: 20050158882
    Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 21, 2005
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Soon-won Hwang, I-hun Song, Geun-young Yeom, Seok-jae Chung
  • Publication number: 20040174740
    Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 9, 2004
    Inventors: Kyu-Mann Lee, Hyun-Jo Kim, Jeong-Hee Park, Tae-Wan Kim, I-Hun Song, Seok-Jae Chung