Abstract: A method of planarizing an insulating layer for a semiconductor device, whereby a semiconductor substrate having a stepped surface due to material layer patterns of various sizes on the surface thereof is prepared. An interlayer insulating layer formed of an organic, low dielectric material covers the stepped surface of the semiconductor substrate. A capping insulating layer is formed on the interlayer insulating layer. A portion of the interlayer insulating layer which is higher than another portion of the interlayer insulating layer is selectively exposed by performing a partial chemical-mechanical polishing process on the capping insulating layer. The exposed portion of the interlayer insulating layer is plasma-processed to a predetermined depth. An entirely planarized interlayer insulating layer is formed by performing a blanket chemical-mechanical polishing process on the plasma processed portion of the interlayer insulating layer and the capping insulating layer.

Abstract: A method for forming contact plugs and simultaneously planarizing a substrate surface in an integrated circuit. Initially, a conductive structure is formed on a semiconductor substrate having a plurality of diffusion regions therein. A first insulating layer is formed over the semiconductor substrate including the conductive structure. The first insulating layer is etched using a contact hole forming mask to form a contact hole. A conductive layer is formed on the first insulating layer filling up the contact hole with the conductive layer. The conductive layer is etched until an upper surface of the first insulating layer is exposed. A second insulating layer is formed over the first insulating layer. A contact plug free of voids is formed and simultaneously a substrate surface is planarized by planarization-etching the second and first insulating layers.

Abstract: A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

Abstract: A method is disclosed for manufacturing a semiconductor device that is capable of minimizing a step difference between DRAM and logic regions of a semiconductor substrate by forming a capacitor in the DRAM cell region and then forming a metal interconnection in the logic region after deposition of a first insulating layer before planarization, the metal interconnection having height similar to the capacitor. Although a second insulating layer is deposited over the substrate, a step between the DRAM cell region and local region can be minimized because of the metal interconnection formed in the logic region. Thus, although only either CMP or etch back process is used, planarization of the second insulating layer is allowed.

Abstract: Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate having a surface thereon and then depositing an electrically insulating layer on the semiconductor substrate, to fill the trench. This depositing step is preferably performed by depositing an electrically insulating layer (e.g., SiO.sub.2) using a plasma chemical vapor. A mask layer is then formed on the electrically insulating layer. According to a preferred aspect of the present invention, the mask layer is planarized using chemical mechanical polishing, for example, to define a mask having openings therein that expose first portions of the electrically insulating layer extending opposite the surface. These first portions are also self-aligned to and extend opposite active portions of the substrate. The exposed portions of the electrically insulating layer are then etched using the mask as an etching mask.