Patents by Inventor Seok Jin JEONG

Seok Jin JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105087
    Abstract: The present disclosure provides a display device for inspecting image data that may include a data processing device configured to generate first cyclic redundancy check (CRC) data for a partial area among areas of image data included in a first frame to transmit the image data of the first frame and the first CRC data and a data driving device configured to receive the image data of the first frame and the first CRC data from the data processing device to generate second CRC data for a partial area among areas of the image data included in the first frame on the basis of the image data of the first frame and to compare the first CRC data with the second CRC data to determine whether there is an error in the partial area among areas of the image data included in the first frame.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 28, 2024
    Applicant: LX SEMICON CO., LTD.
    Inventors: Seok Jin JEONG, Bong Sin KWAK, Man Jung KIM, Myung Yu KIM, Kwang Hee YOON
  • Patent number: 11942551
    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Taek Kim, Seok Hoon Kim, Pan Kwi Park, Moon Seung Yang, Seo Jin Jeong, Min-Hee Choi, Ryong Ha