Abstract: A paste for a reference electrode according to an embodiment of the present disclosure includes silver chloride powder and a carbon-based conductive material. The carbon-based conductive material may include at least one compound selected from the group consisting of carbon nanotubes, graphite, graphene, and carbon black. The reference electrode formed of the paste for a reference electrode according to an exemplary embodiment may provide improved mechanical properties and electrochemical properties.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

Abstract: A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line.

Abstract: A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

Abstract: A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

Abstract: A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line.

Abstract: A sense amplifier may be provided. The sense amplifier may include an amplification circuit and/or a cell current control circuit. The amplification circuit may be configured to compare a voltage level of a signal line with a level of a read voltage. The cell current control circuit may be configured to decrease the voltage level of the signal line based on an output signal.

Abstract: A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.

Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells in which a plurality of columns and a plurality of rows are arranged, a read voltage application circuit configured to apply a read voltage to a selected memory cell of the plurality of resistive memory cells, a sensing circuit configured to detect an amount of a current flowing through the selected memory cell and sense data, and an overcurrent prevention circuit configured to reduce voltage levels at both ends of the selected memory cell when an overcurrent flows through the selected memory cell.

Abstract: A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage.