Patents by Inventor Seok Ling Lim

Seok Ling Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9972589
    Abstract: Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Jiun Hann Sir, Seok Ling Lim, Hoay Tien Teoh
  • Patent number: 9159714
    Abstract: An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a secondary die coupled to the first plurality of contacts; and a carrier including carrier contact points operable for mounting the carrier to a substrate. A method including forming a first portion of a carrier adjacent a device side of a die and including carrier contact points operable for mounting the carrier to a substrate; and forming a second portion including second carrier contact points connected to contacts on the backside of the die or on at least two opposing sidewalls of the die; and coupling a secondary die to the second carrier contact points.
    Type: Grant
    Filed: September 28, 2013
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Choong Kooi Chee, Seok Ling Lim
  • Publication number: 20150091180
    Abstract: An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a secondary die coupled to the first plurality of contacts; and a carrier including carrier contact points operable for mounting the carrier to a substrate. A method including forming a first portion of a carrier adjacent a device side of a die and including carrier contact points operable for mounting the carrier to a substrate; and forming a second portion including second carrier contact points connected to contacts on the backside of the die or on at least two opposing sidewalls of the die; and coupling a secondary die to the second carrier contact points.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 2, 2015
    Inventors: Jenny Shio Yin ONG, Choong Kooi Chee, Seok Ling Lim