Abstract: A method for producing a silicon nanosensor integrated with advanced complementary metal oxide semiconductor (CMOS) logic circuit having gate length (Lg) of less than 0.25 ?m, comprising the steps of: allocating a silicon nanosensor region and a CMOS logic circuit region on one bulk silicon substrate; forming silicon nanowires at the allocated nanosensor region while shielding the CMOS logic circuit region; applying a layer of protecting hardmask on the substrate such that the hardmask acts as an extra protection layer to the nanosensor region while acting as a hardmask for CMOS logic circuit formation process thereinafter; subjecting the substrate to selective etching to form trenches, filling the trenches with silicon oxide and subjecting the substrate to chemical mechanical planarization; and removing the hardmask from the substrate in a region-by-region manner, in which the nanosensor region remains unexposed while removing hardmark from the CMOS logic circuit region, and vice versa.

Abstract: An integrated circuit device that includes a substrate as a base of the integrated circuit device, a semiconductor layer disposed on top of the substrate, an isolation layer disposed on top of the semiconductor layer, a plurality of metals disposed above the isolation layer, a transistor including a source and drain region positioned in the semiconductor layer, and a gate electrode connected to the source and drain region and positioned in the isolation layer, wherein the source and drain region, and gate electrode are respectively connected to the metals by electrical contacts, and a Faraday shield positioned laterally between the gate electrode and the drain region in the isolation layer. The Faraday shield is connected to one of the metals through at least one conductive interconnect produced by a damascene process such that the interconnect forms a continuous connection to the metal from the Faraday shield.