Abstract: A semiconductor device may include a gate structure including stacked local lines and a multi-step structure, wherein the multi-step structure defines pads of the local lines, channel patterns respectively disposed over the pads, a block word line disposed over the channel patterns and extending along a profile of the multi-step structure, and first contact plugs passing through the channel patterns and respectively connecting the channel patterns and the local lines.

Abstract: A semiconductor device may include a source structure, a support structure positioned on the source structure and including a first inclined surface extending in a second direction crossing the first direction, a gate structure positioned on the source structure and the support structure and including conductive layers and insulating layers alternately stacked, channel structures extending through the gate structure and connected to the source structure, and a slit structure extending in the first direction through the gate structure, wherein each of the conductive layers includes a second inclined surface extending in the second direction.

Abstract: A semiconductor device may include: a first gate structure; a second gate structure disposed over the first gate structure; and a channel structure including a first portion extending through the first gate structure, the first portion having a tapered cross section, a second portion having a tapered cross section, and a third portion connecting the first portion with the second portion, wherein the third portion has a vertical profile, and wherein the second portion and the third portion extends through the second gate structure.

Abstract: A memory device includes a first peripheral circuit having first page buffers is functionally divided into a cell region and a connection region. A first memory cell array positioned on the first peripheral circuit includes first bit lines that are electrically connected to the first page buffers. A second memory cell array positioned on the first memory cell array includes second bit lines, which are electrically connected to the first bit lines, respectively. The first peripheral circuit is able to make use of both memory arrays using connections between the two memory arrays.

Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting an a top portion of the first stack structure, a second source line layer directly contacting the first source line layer, a second stack structure contacting the second source line layer and overlapping with the first stack structure in the vertical direction, and a plurality of second slits passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.

Abstract: A memory device may include a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked along a first direction, an opening extending in the first direction from at least one conductive layer, among the plurality of conductive layers, in the stack structure, and a contact plug in the opening. The opening may include a protrusion portion protruding in a second direction intersecting the first direction.

Abstract: A semiconductor device, and a method of manufacturing the same, includes a gate stack including a plurality of conductive lines extending in a first horizontal direction, a first slit and a second slit passing through the gate stack in a vertical direction and extending in the first horizontal direction, and a plurality of cell plugs extending in the vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. Each of the first slit and the second slit includes a first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and a second portion extending in the first horizontal direction.

Abstract: A semiconductor device may include: a gate structure including insulating layers and conductive layers alternately stacked; first supports located in the gate structure, each first support including a second channel layer; second supports located in the gate structure, each second support including a barrier layer; and contact structures extending between the second supports through the gate structure, wherein each contact structure is connected to a corresponding conductive layer.

Abstract: A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.

Abstract: In a method of manufacturing a semiconductor device, an additional, induced-stress-limiting structure may be provided on a surface, which opposes stress that can be induced in a semiconductor device during its manufacturing processes. Such a stress compensation layer may be formed on a surface to compensate a stress applied to the rest of structure.

Abstract: A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.

Abstract: A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.

Abstract: A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.

Abstract: There are provided a memory device and a manufacturing method of a memory device. The memory device includes a plurality of conductive layers, support structures penetrating the plurality of conductive layers, a contact hole exposing any one of the plurality of conductive layers and any one of the plurality of support structures, and a contact disposed in the contact hole.

Abstract: There are provided a memory device and a manufacturing method thereof. The memory device includes: a first stack structure including a plurality of first interlayer insulating layers and a plurality of conductive layers for first word lines, which are alternately stacked; and a second stack structure including a plurality of second interlayer insulating layers and a plurality of conductive layers for second word lines, which are alternately stacked; a first etch stop layer disposed between the first stack structure and the second stack structure; and a plurality of first word line contacts extending to the inside of the first stack structure through the second stack structure and the first etch stop layer.

Abstract: A semiconductor device may include: a gate structure including conductive layers and insulating layers that are alternately stacked. Tapered supports formed in the gate structure layers have a first width at a first level of the layers and a second width smaller than the first width at a second level of the layers. A tapered contact structure is located between the tapered supports in the gate structure having a third width at the first level and a fourth width larger than the third width at the second level. The gate structure taper and the contact structure taper are “mirror images” of each other.

Abstract: A semiconductor device includes a supporter including a plurality of stairs, a gate structure including gate lines that are stacked on the supporter, wherein the gate lines include pads, and the pads are disposed over the plurality of stairs, first contact plugs that are connected to the pads, and channel structures that extend through the gate structure.

Abstract: A semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of th

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a first cell area and a second cell area adjacent to each other in a first direction, a support disposed between the first cell area and the second cell area, first gate lines stacked in the first cell area, first pads configured to extend from the first gate lines and configured to protrude upward along a first sidewall of the support, second gate lines stacked in the second cell area, second pads configured to extend from the second gate lines and configured to protrude upward along a second sidewall of the support, and first connection pads configured to extend in the first direction along a third sidewall of the support and configured to electrically connect the first pads with the second pads.

Abstract: A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.