Abstract: A display device is provided. The display device includes a substrate including a display area and a non-display area, an insulating layer above the substrate, and in the display area and the non-display area, and at least one dam in the non-display area, surrounding the display area, and including a lower dam layer above the substrate, an intermediate dam layer above the lower dam layer, and an upper dam layer covering the lower dam layer and the intermediate dam layer, wherein the insulating layer is between the intermediate dam layer and the upper dam layer.

Abstract: A display device comprises a substrate, a pixel electrode, a common electrode, an intermediate layer, a semiconductor layer, a metal layer, and an organic layer. The substrate includes an opening area, a peripheral area surrounding the opening area, and a display area surrounding the peripheral area. The pixel electrode overlaps the display area. The common electrode overlaps the pixel electrode. The intermediate layer is disposed between the pixel electrode and the common electrode and includes a light emitting layer and a functional layer. The semiconductor layer overlaps the peripheral area and is spaced from the display area. The metal layer overlaps the semiconductor layer. The organic layer is disposed between the semiconductor layer and the metal layer. The common electrode, the functional layer, and the metal layer respectively have a first opening, a second opening, a third opening overlapping each other and overlapping the semiconductor layer.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device may include a first interlayer insulating film containing therein a plurality of pores, a first line structure in the first interlayer insulating film, an inserted insulating film extending along and on a upper surface of the first interlayer insulating film and in contact with the first interlayer insulating film, a barrier insulating film in contact with the inserted insulating film and extending along an upper surface of the inserted insulating film and an upper surface of the first line structure, a second interlayer insulating film on the barrier insulating film and a second line structure disposed in the second interlayer insulating film and connected to the first line structure.

Abstract: A stable liquid pharmaceutical formulation according to the present invention includes an antibody or antigen-binding fragment thereof, a surfactant, a sugar or a sugar derivative, a buffer, and a stabilizer. The stable liquid pharmaceutical formulation according to the present invention has low viscosity not only when antibody content is low but also when antibody content is high, and exhibits superior long-term storage stability based on superior stability observed under accelerated conditions and harsh conditions.

Abstract: Disclosed are a BCC dual phase refractory superalloy with high phase stability and a manufacturing method therefor, the alloy comprising one or more of Ti, Zr, and Hf as Group 4 transition metals, one or more of Nb and Ta as Group 5 transition metals, and Al, and having a structure of a BCC phase, wherein the BCC phase is composed of a disordered BCC phase and an ordered BCC phase, and wherein the ordered BCC phase is formed by allowing Al, which is a BCC phase forming element, to be soluted in an area of the BCC phase where the contents of the Group 5 transition metals are more than those of the Group 4 transition metals, so that the present disclosure provides a BCC dual phase refractory superalloy with high phase stability, characterized in that when a BCC dual phase with the ordered BCC phase and the disordered BCC phase separated from each other is formed by aging, the aging condition is precisely cont rolled through the apex temperature (Tc) of the BCC phase miscibility gap, expressed by (Equation 1) be

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A display panel includes a first display area including first light emitting areas and a second display area adjacent to the first display area and including second light emitting areas and a signal transmission area; a base substrate; a circuit element layer disposed on the base substrate; a light blocking pattern disposed between the base substrate and the circuit element layer, overlapping the first and second light emitting areas, and having a first opening corresponding to the signal transmission area; and a light emitting element layer disposed on the circuit element layer and including a first electrode overlapping the first and second light emitting areas, a light emitting layer disposed on the first electrode, and a second electrode overlapping the first and second light emitting areas. The signal transmission area has a second transmittance that is higher than a first transmittance of the second light emitting areas.

Abstract: A computed tomography (CT) apparatus includes a gantry including a rotation device which has a ring shape and is rotatable about an axis of rotation, a plurality of light sources configured to emit X-rays to a subject, at least one detector provided on the rotation device and configured to detect X-rays passing through the subject, and one or more processors. The at least one processors are configured to rotate the rotation device in a first rotation direction by an angle of rotation determined based on a total number of the plurality of light sources, emit X-rays to the subject and detect X-rays passing through the subject during the rotation of the rotation device in the first rotation direction, and rotate the rotation device by the determined rotation angle in a second rotation direction.

Abstract: A computing device can receive a first measured touch value, the first measured touch value indicating first touch input at a first location near a camera included in the computing device, receive a second measured touch value, the second measured touch value indicating second touch input at a second location farther from the camera than the first location, a density of touch sensors in the second location being greater than a density of touch sensors in the first location, generate a first compensated touch value based on the first measured touch value and a first scaling value, generate a second compensated touch value based on the second measured touch value and a second scaling value, the second scaling value being less than the first scaling value, and process the first touch input and the second touch input based on the first compensated touch value and the second compensated touch value.

Abstract: An antenna device according to an embodiment of the present invention includes a dielectric layer, a radiation pattern disposed on a top surface of the dielectric layer, a signal pad electrically connected to the radiation pattern, and a ground pad spaced apart from the signal pad and having an isolation space. A length of the isolation space is greater than a length of the signal pad.

Abstract: The present disclosure relates to a microorganism expressing active D-proline reductase.

Abstract: A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

Abstract: The present disclosure proposes an apparatus for determining an intestinal microbiome index. The apparatus according to the present disclosure may: obtain test information about a biological sample of a subject from a test apparatus; determine, based on the test information, first information about the similarity of intestinal microflora, second information about a proportion of harmful intestinal microflora, third information about a proportion of beneficial intestinal microflora, and/or fourth information about the diversity of intestinal microflora; and determine an intestinal microbiome index indicating a state of intestinal microbiome of the subject based on the determined information.

Abstract: An imaging pixel design is provide with a photo-sensor block structure that facilitates dynamic control of well capacity in the photodiode region (i.e., a “well capacity adjustment (WCA) gate photo-sensor block”). The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.

Abstract: A display device includes: a timing controlling part generating an image data, a data control signal and a gate control signal; a data driving part generating a data voltage using the image data and the data control signal; a gamma part transmitting the data voltage corresponding to the image data; a gate driving part generating a gate voltage using the gate control signal; a display panel including subpixels, gate lines, left data lines at a left side of the subpixels and right data lines at a right side of the subpixels; and first MUX switches, second MUX switches, third MUX switches, fourth MUX switches, fifth MUX switches and sixth MUX switches sequentially transmitting the data voltage to the left data lines and the right data lines.