Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: A memory card including a memory controller, a memory system and a method to control a memory are provided. The memory card includes a flash memory, a memory interface outputting a writing data signal to be written into the flash memory, and a multi-level converter transforming the writing data signal into a writing voltage signal to be provided to the flash memory. The writing voltage signal has one of different voltage levels in accordance with plural bits of the writing data signal.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: A memory card including a memory controller, a memory system and a method to control a memory are provided. The memory card includes a flash memory, a memory interface outputting a writing data signal to be written into the flash memory, and a multi-level converter transforming the writing data signal into a writing voltage signal to be provided to the flash memory. The writing voltage signal has one of different voltage levels in accordance with plural bits of the writing data signal.

Abstract: Computer systems and related methods are provided for managing connections to storage devices. The computer system includes a connector and a register. The connector includes a plurality of pins configured to be removably connected to a first storage device and to a second storage device. A first pin of the connector carries a signal that indicates when the connector is connected to the first storage device, and a second pin carries a signal that indicates when the connector is connected to the second storage device. The register stores connection information that indicates whether the first storage device and/or the second storage device are connected to the connector.

Abstract: A memory card including a pad, a drive circuit activating the pad in accordance with an input signal, and a controller regulating a drive voltage level and a drive point of an output signal generated from the drive circuit in accordance with a voltage level of the output signal of the drive circuit. The controller may include a delay circuit, generating a second clock signal by delaying a first clock signal provided from an external source and generating a second clock signal from the first clock signal. The controller may further include a detection circuit capturing the voltage level of the output signal of the drive circuit as a first detection voltage in sync with the first clock signal and capturing the voltage level of the output signal of the drive circuit as a second detection voltage in sync with the second dock signal.

Abstract: A memory device including a connector for independently interfacing a host and memory devices using a multimedia card (MMC) protocol is provided. The memory device includes an internal bus and a connector. The internal bus is configured to receive a command or data from the host via a plurality of input/output pins. The connector is electrically connected with the internal bus and connected with another memory device, which interfaces with the host through the internal bus using the MMC protocol.

Abstract: A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error and a plurality of subsequent read data without outputting. The storing of the data is performed during the performing of the error correction operation.

Abstract: A flash memory card including a main memory core, a removable supplementary memory core, and a controller operating to control the main and supplementary memory cores. The supplementary memory core includes a plurality of memory cores and is replaceable.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: A memory card including a pad, a drive circuit activating the pad in accordance With an input signal, and a controller regulating a drive voltage level and a drive point of an output signal generated from the drive circuit in accordance with a voltage level of the output signal of the drive circuit. The controller may include a delay circuit, generating a second clock signal by delaying a first clock signal provided from an external source and generating a second clock signal from the first clock signal. The controller may further include a detection circuit capturing the voltage level of the output signal of the drive circuit as a first detection voltage in sync with the first clock signal and capturing the voltage level of the output signal of the drive circuit as a second detection voltage in sync with the second dock signal.

Abstract: Computer systems and related methods are provided for managing connections to storage devices. The computer system includes a connector and a register. The connector includes a plurality of pins configured to be removably connected to a first storage device and to a second storage device. A first pin of the connector carries a signal that indicates when the connector is connected to the first storage device, and a second pin carries a signal that indicates when the connector is connected to the second storage device. The register stores connection information that indicates whether the first storage device and/or the second storage device are connected to the connector.