Patents by Inventor Seok-Woo Choi
Seok-Woo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128022Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer includes a plurality of grains and grain boundaries disposed between adjacent grains. The grain boundary includes a secondary phase including Sn, a rare-earth element, and a first subcomponent. The rare-earth element includes at least one of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, Tb, Tm, La, Gd and Yb. The first subcomponent includes at least one of Si, Mg, and Al.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Chang Hak Choi, Seok Hyun Yoon, Ki Yong Lee, Jong Myeong Jeon
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Patent number: 11927890Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.Type: GrantFiled: August 22, 2022Date of Patent: March 12, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Heo, Cha Won Koh, Sang Joon Hong, Hyun Woo Kim, Kyung-Won Kang, Dong-Wook Kim, Kyung Won Seo, Young Il Jang, Yong Suk Choi
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Publication number: 20240022263Abstract: A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.Type: ApplicationFiled: November 15, 2022Publication date: January 18, 2024Inventor: Seok Woo CHOI
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Patent number: 11521696Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.Type: GrantFiled: October 22, 2020Date of Patent: December 6, 2022Assignee: SK hynix Inc.Inventors: Young Jun Park, Young Jun Ku, Myeong Jae Park, Ji Hwan Park, Seok Woo Choi
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Publication number: 20210295938Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.Type: ApplicationFiled: October 22, 2020Publication date: September 23, 2021Applicant: SK hynix Inc.Inventors: Young Jun PARK, Young Jun KU, Myeong Jae PARK, Ji Hwan PARK, Seok Woo CHOI
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Patent number: 10678716Abstract: A memory device includes: a plurality of first control signal interfaces respectively corresponding to a plurality of channels, and suitable for receiving control signals from a host; a plurality of first data interfaces respectively corresponding to the plurality of channels, and suitable for exchanging data and data strobe signals with the host; a second control signal interface suitable for receiving control signals through a selected one of the first control signal interfaces and a selected one of the channels and outputting the received control signals, in a monitoring mode; and a second data interface suitable for receiving a part of the data and data strobe signals exchanged through a selected one of the first data interfaces and the selected channel, and outputting the received part of the data and data strobe signals, in the monitoring mode.Type: GrantFiled: December 28, 2018Date of Patent: June 9, 2020Assignee: SK hynix Inc.Inventors: Myeong-Jae Park, Seok-Woo Choi, Young-Jae Choi
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Publication number: 20190294566Abstract: A memory device includes: a plurality of first control signal interfaces respectively corresponding to a plurality of channels, and suitable for receiving control signals from a host; a plurality of first data interfaces respectively corresponding to the plurality of channels, and suitable for exchanging data and data strobe signals with the host; a second control signal interface suitable for receiving control signals through a selected one of the first control signal interfaces and a selected one of the channels and outputting the received control signals, in a monitoring mode; and a second data interface suitable for receiving a part of the data and data strobe signals exchanged through a selected one of the first data interfaces and the selected channel, and outputting the received part of the data and data strobe signals, in the monitoring mode.Type: ApplicationFiled: December 28, 2018Publication date: September 26, 2019Inventors: Myeong-Jae PARK, Seok-Woo CHOI, Young-Jae CHOI
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Patent number: 9310125Abstract: A refrigerator includes a body provided with a storage compartment having a front side opening, a door rotatably coupled by a coupling member to one side of the body to open/close the front side opening of the storage compartment; and at least one door pocket coupled to an inner side of the door in a way to have a storage space and provided with a first side surface and a second side surface, the second side surface provided at a side facing the storage compartment and the first side surface connected to the second side surface to be positioned adjacent to a side of the door that is open. The second side surface is formed at a position higher than a position of the first side surface to prevent cool air from leaking outside, and stored goods positioned in the storage space are withdrawn through the first side surface.Type: GrantFiled: June 25, 2014Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Won Kim, Amitoj Singh, Seok Woo Choi, Jin Jeong, Hyung Yong Choi
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Publication number: 20150035426Abstract: A refrigerator includes a body provided with a storage compartment having a front side opening, a door rotatably coupled by a coupling member to one side of the body to open/close the front side opening of the storage compartment; and at least one door pocket coupled to an inner side of the door in a way to have a storage space and provided with a first side surface and a second side surface, the second side surface provided at a side facing the storage compartment and the first side surface connected to the second side surface to be positioned adjacent to a side of the door that is open. The second side surface is formed at a position higher than a position of the first side surface to prevent cool air from leaking outside, and stored goods positioned in the storage space are withdrawn through the first side surface.Type: ApplicationFiled: June 25, 2014Publication date: February 5, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Won KIM, Amitoj SINGH, Seok Woo CHOI, Jin JEONG, Hyung Yong CHOI
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Patent number: 8411517Abstract: A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.Type: GrantFiled: March 4, 2010Date of Patent: April 2, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Seok-Woo Choi
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Patent number: 8203860Abstract: A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.Type: GrantFiled: August 3, 2009Date of Patent: June 19, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-young Chung, Yang-ki Kim, Seok-woo Choi
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Patent number: 8149015Abstract: A transceiver system includes a first semiconductor device having a first input/output (I/O) pad connected with an I/O channel and a second semiconductor device having a second I/O pad connected with the I/O channel. The first semiconductor device is configured to terminate the first I/O pad with a first voltage when data is received, and maintain the first I/O pad and the I/O channel at the first voltage when data is transmitted. The second semiconductor device is configured to terminate the second I/O pad with a second voltage higher than the first voltage when data is received, and maintain the second I/O pad and the I/O channel at the second voltage when data is transmitted.Type: GrantFiled: July 12, 2010Date of Patent: April 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Seok-Woo Choi
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Publication number: 20110057684Abstract: A transceiver system includes a first semiconductor device having a first input/output (I/O) pad connected with an I/O channel and a second semiconductor device having a second I/O pad connected with the I/O channel. The first semiconductor device is configured to terminate the first I/O pad with a first voltage when data is received, and maintain the first I/O pad and the I/O channel at the first voltage when data is transmitted. The second semiconductor device is configured to terminate the second I/O pad with a second voltage higher than the first voltage when data is received, and maintain the second I/O pad and the I/O channel at the second voltage when data is transmitted.Type: ApplicationFiled: July 12, 2010Publication date: March 10, 2011Inventor: Seok-Woo CHOI
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Publication number: 20100226189Abstract: A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.Type: ApplicationFiled: March 4, 2010Publication date: September 9, 2010Inventor: Seok-Woo Choi
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Publication number: 20100110749Abstract: A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.Type: ApplicationFiled: August 3, 2009Publication date: May 6, 2010Inventors: Hae-young Chung, Yang-ki Kim, Seok-woo Choi
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Patent number: 7642811Abstract: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT (Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.Type: GrantFiled: January 25, 2008Date of Patent: January 5, 2010Assignee: Hynix Semidonductor Inc.Inventors: Seok-Woo Choi, Hong-June Park
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Patent number: 7508881Abstract: Provided are a current mode differential transmission method and system for differentially transmitting three units of data using four signal lines. The method includes: dividing the four signal lines 1a, 1b, 2a and 2b into two pairs of signal lines 1a/1b and 2a/2b, and differentially transmitting respective data (first data and second data) via the two pairs of signal lines 1a/1b and 2a/2b; and transmitting the other data (third data) by differentially changing common mode currents of the two pairs of signal lines 1a/1b and 2a/2b.Type: GrantFiled: June 2, 2005Date of Patent: March 24, 2009Assignee: Postech Academy-Industrial FoundationInventors: Seok Woo Choi, Hong June Park
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Publication number: 20090002031Abstract: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT (Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.Type: ApplicationFiled: January 25, 2008Publication date: January 1, 2009Inventors: Seok-Woo Choi, Hong-June Park
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Patent number: 7339409Abstract: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.Type: GrantFiled: December 21, 2004Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventors: Seok-Woo Choi, Hong-June Park
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Publication number: 20050195005Abstract: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.Type: ApplicationFiled: December 21, 2004Publication date: September 8, 2005Inventors: Seok-Woo Choi, Hong-June Park