Abstract: Disclosed is a data storing method performed by a controller. The method includes storing an attribute value of first data to be written to a nonvolatile memory device in a command queue, determining whether the first data is garbage collection data on the basis of the attribute value when a power interruption occurs, and writing the first data to the nonvolatile memory device according to a result of the determination of whether the first data is garbage collection data or not.

Abstract: Disclosed is a method of operating a storage device including a NAND flash memory including memory cells grouped into blocks, each block being divided into pages. According to the method, a controller in the storage device loads, onto a memory region, a look-up table containing first read reference voltage sets corresponding to respective retention degradation stages of the NAND flash memory and second read reference voltages sets corresponding to respective pages which vary in terms of the threshold voltages. Subsequently, the controller performs a read operation on the memory cells on a per-block basis by using the first read reference voltage set corresponding to a current retention degradation stage, the second read reference voltage set corresponding to a current page, or both, until all of the memory cells in a current block are correctly read.

Abstract: A light-emitting storage device and a light-emitting control method are provided. The device includes a storage device controller, a processor, and at least one light-emitting unit. The storage device controller is electrically connected to a host through a host controller interface for controlling the access of the light-emitting storage device. The processor is electrically connected to the storage device controller to connect to the host. The at least one light-emitting unit is electrically connected to the processor. When the host transmits a control signal to the storage device controller through the host controller interface and the control signal is judged as a signal for controlling the at least one light-emitting unit by the storage device controller, the storage device controller transmits the control signal to the processor to control a light-emitting mode of the at least one light-emitting unit.

Abstract: A non-volatile memory system includes a NAND flash memory device including at least one NAND flash memory and a memory controller that controls the NAND flash memory, a host device including a file system and a host controller that receives a command from the file system to provide the command to the NAND flash memory device, and a save storage manager that monitors a number and location of run-time bad blocks in the NAND flash memory, monitors a logical address use-state of the file system, and reduces a logical address space which the file system is able to use as the number of the run-time bad blocks is increased.

Abstract: An asynchronous NAND-type memory device includes a circuit configured to perform an operation based on a signal, a first pin configured to obtain an operation control signal, a second pin configured to output a data output reference signal, and a third pin configured to output data in synchronization with the data output reference signal. The circuit is provided such that the first pin obtains, from the external device, the operation control signal that is transitioned at a second time point after a first time point at which the memory device enters into a ready state, the second pin outputs the data output reference signal, which is transitioned at a third time point that is later than the second time point by a predetermined time interval, and the third pin outputs the data in synchronization with the operation control signal which is periodically transitioned, from the third time point.

Abstract: Disclosed is a method of operating a storage device including a NAND flash memory including memory cells grouped into blocks, each block being divided into pages. According to the method, a controller in the storage device loads, onto a memory region, a look-up table containing first read reference voltage sets corresponding to respective retention degradation stages of the NAND flash memory and second read reference voltages sets corresponding to respective pages which vary in terms of the threshold voltages. Subsequently, the controller performs a read operation on the memory cells on a per-block basis by using the first read reference voltage set corresponding to a current retention degradation stage, the second read reference voltage set corresponding to a current page, or both, until all of the memory cells in a current block are correctly read.

Abstract: An asynchronous NAND-type memory device includes a circuit configured to perform an operation based on a signal, a first pin configured to obtain an operation control signal, a second pin configured to output a data output reference signal, and a third pin configured to output data in synchronization with the data output reference signal. The circuit is provided such that the first pin obtains, from the external device, the operation control signal that is transitioned at a second time point after a first time point at which the memory device enters into a ready state, the second pin outputs the data output reference signal, which is transitioned at a third time point that is later than the second time point by a predetermined time interval, and the third pin outputs the data in synchronization with the operation control signal which is periodically transitioned, from the third time point.

Abstract: A light-emitting storage device and a light-emitting control method are provided. The device includes a storage device controller, a processor, and at least one light-emitting unit. The storage device controller is electrically connected to a host through a host controller interface for controlling the access of the light-emitting storage device. The processor is electrically connected to the storage device controller to connect to the host. The at least one light-emitting unit is electrically connected to the processor. When the host transmits a control signal to the storage device controller through the host controller interface and the control signal is judged as a signal for controlling the at least one light-emitting unit by the storage device controller, the storage device controller transmits the control signal to the processor to control a light-emitting mode of the at least one light-emitting unit.

Abstract: Disclosed is a data storing method performed by a controller. The method includes storing an attribute value of first data to be written to a nonvolatile memory device in a command queue, determining whether the first data is garbage collection data on the basis of the attribute value when a power interruption occurs, and writing the first data to the nonvolatile memory device according to a result of the determination of whether the first data is garbage collection data or not.

Abstract: A non-volatile memory system includes a NAND flash memory device including at least one NAND flash memory and a memory controller that controls the NAND flash memory, a host device including a file system and a host controller that receives a command from the file system to provide the command to the NAND flash memory device, and a save storage manager that monitors a number and location of run-time bad blocks in the NAND flash memory, monitors a logical address use-state of the file system, and reduces a logical address space which the file system is able to use as the number of the run-time bad blocks is increased.

Abstract: Provided is a memory card, which includes two pairs of opposite edges, first row terminals arranged adjacent to an insertion-side edge of the memory card, and second row terminals arranged apart from the insertion-side edge of the memory card. The memory card can be easily reset in terms of software without controlling power supply in terms of hardware. Also, the memory card can be smoothly attached and detached during insertion of the memory card into a socket and reduce damage to a device.

Abstract: Provided is a memory card, which includes two pairs of opposite edges, first row terminals arranged adjacent to an insertion-side edge of the memory card, and second row terminals arranged apart from the insertion-side edge of the memory card. The memory card can be easily reset in terms of software without controlling power supply in terms of hardware. Also, the memory card can be smoothly attached and detached during insertion of the memory card into a socket and reduce damage to a device.

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract: Memory card adapters and/or a memory apparatuses may be provided. For example, a memory card adapter including a main housing section that corresponds to a memory card socket of a first standard, the main housing section including a card housing section, the card housing section configured to house a memory card of a second standard different from the first standard therein, a first surface of the main housing section defining a through-hole, the through-hole configured to expose a connection pin of the memory card to be housed in the housing section to an outside of the housing section, and a second surface of the main housing section defining a card insertion hole, the second surface being different from the first surface, the card insertion hole configured to receive the memory card into the card housing section may be provided.

Abstract: Provided is a memory card, which includes two pairs of opposite edges, first row terminals arranged adjacent to an insertion-side edge of the memory card, and second row terminals arranged apart from the insertion-side edge of the memory card. The memory card can be easily reset in terms of software without controlling power supply in terms of hardware. Also, the memory card can be smoothly attached and detached during insertion of the memory card into a socket and reduce damage to a device.

Abstract: Memory card adapters and/or a memory apparatuses may be provided. For example, a memory card adapter including a main housing section that corresponds to a memory card socket of a first standard, the main housing section including a card housing section, the card housing section configured to house a memory card of a second standard different from the first standard therein, a first surface of the main housing section defining a through-hole, the through-hole configured to expose a connection pin of the memory card to be housed in the housing section to an outside of the housing section, and a second surface of the main housing section defining a card insertion hole, the second surface being different from the first surface, the card insertion hole configured to receive the memory card into the card housing section may be provided.

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.