Abstract: An organic light emitting device including: a substrate; a first electrode; a second electrode; and an organic layer interposed between the first electrode and the second electrode and including an emission layer, wherein one of the first electrode and the second electrode is a reflective electrode and the other is a semitransparent or transparent electrode, and wherein the organic layer includes a layer having at least one of the compounds having at least one carbazole group, and a flat panel display device including the organic light emitting device. The organic light emitting device has low driving voltage, excellent current density, high brightness, excellent color purity, high efficiency, and long lifetime.

Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.

Abstract: Devices, systems, and methods for evaluating the viability of embryos are disclosed. In particular, devices, systems, and methods for measuring internal and external pH of an embryo, electrolytes, and oxidative stress markers for evaluating developmental potential of an embryo are provided. The methods disclosed herein should improve in vitro fertilization (IVF) outcomes by reducing inadvertent transfer of non-viable embryos.

Abstract: A coil electronic component includes a body including a coil portion therein, and including a plurality of magnetic particles including an Fe-based alloy component, and an external electrode connected to the coil portion, wherein at least a portion of the plurality of magnetic particles include a first layer formed on a surface, and a second layer formed on a surface of the first layer, wherein the first layer includes an Fe oxide component and has a thickness of 10 nm or less.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: Provided is a ceramic catalyst which may include a nanostructure composed of ionic salts; and catalyst particles attached to the surface of the nanostructure.

Abstract: Disclosed are an apparatus and method for detecting dementia and providing a dementia patient management service.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: Provided is a method for sharing a photograph based on voice recognition in an aspect. The method may include obtaining an image for a photograph taken using a camera; obtaining voice data associated with the obtained image; generating a text by recognizing the obtained voice data; associating and storing the obtained image, the obtained voice data and the generated text; and outputting the store image together with at least one of the stored voice data and the stored text.

Abstract: Provided are a cathode substrate, a high capacity all-solid-state battery, and a method for manufacturing the same. The cathode substrate includes a base in a mesh form and a cathode formed on the base, wherein the cathode is configured to overlap the base. The present invention may resolve a conventional problem of deterioration in battery efficiency, which has been caused by a long distance between an electrode and a cathode, and may produce a high capacity all-solid-state battery while suppressing or preventing an increase in the thickness of the cathode.

Abstract: Provided is a ceramic catalyst which may include a nanostructure composed of ionic salts; and catalyst particles attached to the surface of the nanostructure.

Abstract: Disclosed are an apparatus and method for detecting dementia and providing a dementia patient management service.

Abstract: Provided are a cathode substrate, a high capacity all-solid-state battery, and a method for manufacturing the same. The cathode substrate includes a base in a mesh form and a cathode formed on the base, wherein the cathode is configured to overlap the base. The present invention may resolve a conventional problem of deterioration in battery efficiency, which has been caused by a long distance between an electrode and a cathode, and may produce a high capacity all-solid-state battery while suppressing or preventing an increase in the thickness of the cathode.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: An apparatus and method of implementing haptic-based networked virtual environments supporting high-resolution tiled displays. A haptic rendering process of detecting collision between a user of a haptic-device over a virtual environment and each of at least one virtual object and providing a physical force corresponding to a detection result to the haptic-device is performed, and a graphic rendering process of converting each virtual object represented as 3-D data into an object stream represented as 2-D data such that each virtual object is displayed as a 2-D image, and assigning a priority and a frame rate to each converted object stream according to a preset assignment criterion is performed. A plurality of displays provide a display image, including object streams of the virtual objects and background pixels, so that a virtual environment allowing the user of the haptic-device to visually and tactilely immerse thereto is effectively realized by utilizing limited resources.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.