Abstract: The present invention provides an apparatus for inspecting a welding state in a welded portion for an electronic or mechanical coupling in a lithium secondary battery, the apparatus including: a measuring unit configured to obtain data for deriving a resistance value of the welded portion by allowing a resistance measuring probe to contact the welded portion; and a controller configured to communicate with the measuring unit, determine the resistance value of the welded portion by receiving the data obtained from the measuring unit, and determine whether a weak welding was performed by comparing the determined resistance value with a threshold resistance value, in which the measuring unit is configured to allow the resistance measuring probe to contact one end and the other end of the welded portion.

Abstract: In a driving video recording system and a manufacturing method of the same, the driving video recording system includes a camera module for monitoring the surroundings of a vehicle; then first memory for storing a video transmitted from the camera module; the second memory for storing a computer program for controlling the storage of the video; and a controller including a processor for executing the computer program, wherein the computer program includes a contamination classification deep training network model, and the processor is configured to determine whether video data obtained by the camera module through the deep-learning network model is contaminated through the execution of the computer program.

Abstract: Discussed is a battery movement detection apparatus that may include a speed sensor configured to obtain speed information of a tray accommodating a battery, a power supply unit configured to provide a driving power, an environment sensor configured to obtain environment information about a surrounding environment of the battery movement detection apparatus, a communication unit configured to transmit the speed information to a battery position detection apparatus, and a controller configured to calculate an available limit of the power supply unit based on the environment information and control an operation of the communication unit based on the available limit of the power supply unit.

Abstract: This invention relates to a positive photosensitive resin composition that includes a siloxane copolymer of two kinds of reactive silane compounds with specific structures wherein residual impurities such as unreacted monomers and catalysts are minimized, and a UV absorber including one or more kinds of phenol hydroxyl groups capable of crosslinking and an alkoxy group. Accordingly, the resin composition exhibits excellent performances such as sensitivity, resolution, and degree of planarization, and also has excellent weatherability and UV absorbance, thereby providing excellent panel reliability.

Abstract: The present invention relates to a test handler for graphics chip including a loading unit performing a loading process of loading a graphics chip which is to be tested, an unloading unit performing an unloading process of unloading a tested graphics chip, a test unit testing the graphics chip which is to be tested, a buffer unit transferring a graphics chip between the loading unit and the test unit and transferring a graphics chip between the unloading unit and the test unit, wherein the test unit includes a commercial graphics card which is the same as a practically used graphics card and a contact unit connecting the commercial graphics card to the graphics chip which is to be tested.

Abstract: According to an embodiment of the present invention, disclosed is a camera apparatus comprising: a substrate; a light emitting part; a light receiving part comprising an image sensor located on the substrate; and a controller that controls the optical part or the light source using an output value received from a photodetector, wherein the light emitting part comprises: a light source located on the substrate; a holder located on the substrate; an optical part located on the light source; a driving part that moves the optical part along an optical axis; and the photodetector located on the substrate.

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

Abstract: A wet etching apparatus includes a process bath having an internal space configured to receive an etchant and having a support unit, on which a wafer is disposed to be in contact with the etchant. A laser unit is disposed above the process bath and is configured to direct a laser beam to the wafer and to heat the wafer thereby. An etchant supply unit is configured to supply the etchant to the internal space of the process bath.

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

Abstract: A wafer cleaning apparatus is provided. The wafer cleaning apparatus includes comprising a chamber configured to be loaded with a wafer, a nozzle on the wafer and configured to provide liquid chemicals on an upper surface of the wafer, a housing under the wafer, a laser module configured to irradiate laser on the wafer, a transparent window disposed between the wafer and the laser module, and a controller configured to control on/off of the laser module, wherein the controller is configured to control repetition of turning the laser module on and off, and retain temperature of the wafer within a temperature range, and a ratio of time when the laser module is on in one cycle including on/off of the laser module is 30% to 50%.

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

Abstract: There is provided a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes an active pattern extending in a first direction, and a plurality of gate structures spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode extending in a second direction and a gate spacer on a sidewall of the gate electrode and a source/drain pattern disposed between adjacent gate structures. The gate structure comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern.

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

Abstract: A semiconductor device includes: first and second channel structures spaced apart from each other in a first direction; and a source/drain pattern, between the first and second channel structures, including a first interface contacting the first channel structure and a second interface contacting the second channel structure, wherein, in a plan view, the source/drain pattern includes first and second side walls opposite to each other in a second direction, the first side wall includes a first sloped side wall, a second sloped side wall, and a first horizontal intersection at which the first and second sloped side walls meet, a width of the first interface is different from a width of the second interface, in the second direction, and a distance from the first interface to the first horizontal intersection is greater than a distance from the second interface to the first horizontal intersection, in the first direction.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.