Abstract: A display device includes a substrate and a transistor disposed on the substrate and including a semiconductor layer, wherein the semiconductor layer includes a mesh structure, and wherein a plurality of openings are formed in the semiconductor layer.

Abstract: A simple urine flow test result learning method and a lower urinary tract symptom diagnosis method is provided, and more particularly, a simple urine flow test result learning method and a lower urinary tract symptom diagnosis method of training a neural network using simple urine flow test results, which are non-invasive data, and diagnosing lower urinary tract symptoms using the trained neural network, wherein the lower urinary tract symptom diagnosis method prevents pain and shame from occurring in a patient during a diagnosis process of lower urinary tract symptoms and reduces the risk of secondary infection occurring through an invasive diagnosis method, by generating a trained model using results of a simple urine flow test, which is a non-invasive test method, based on deep learning, and diagnosing lower urinary tract symptoms using the trained model.

Abstract: A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.

Abstract: A display device according to an embodiment includes: a substrate; a first conductive layer positioned on the substrate; a semiconductor layer positioned on the first conductive layer; a second conductive layer positioned on the semiconductor layer; an oxygen supply layer positioned under the second conductive layer, in contact with the second conductive layer, and having the same planar shape as the second conductive layer; and a light-emitting element connected to the second conductive layer, wherein the oxygen supply layer includes a metal oxide that includes one or more of indium, zinc, tin, or gallium, or alloys thereof.

Abstract: A display device includes a substrate and a transistor disposed on the substrate and including a semiconductor layer, wherein the semiconductor layer includes a mesh structure, and wherein a plurality of openings are formed in the semiconductor layer.

Abstract: A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

Abstract: A thin film transistor substrate includes a gate electrode disposed on a base substrate, an active pattern overlapping the gate electrode, a source metal pattern including both a source electrode disposed on the active pattern and a drain electrode spaced apart from the source electrode, a buffer layer disposed on the source metal pattern and contacting the active pattern, a first passivation layer disposed on the buffer layer and a second passivation layer disposed on the first passivation layer. The density of hydrogen in the buffer layer is greater than the density of hydrogen in the first passivation layer and less than the density of hydrogen in the second passivation layer.

Abstract: A thin film transistor substrate includes a gate electrode disposed on a base substrate, an active pattern overlapping the gate electrode, a source metal pattern including both a source electrode disposed on the active pattern and a drain electrode spaced apart from the source electrode, a buffer layer disposed on the source metal pattern and contacting the active pattern, a first passivation layer disposed on the buffer layer and a second passivation layer disposed on the first passivation layer. The density of hydrogen in the buffer layer is greater than the density of hydrogen in the first passivation layer and less than the density of hydrogen in the second passivation layer.

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.