Abstract: A quantum circuit simulation device comprising, a memory, a processor operatively connected to the memory, wherein the processor, calculates the weight of a first quantum circuit including at least two qubits and multi-gates connecting the at least two qubits, determines a cutting line that minimizes the number of cuts in the multi-gates based on the weight when dividing the at least two qubits into two groups, determines a second quantum circuit by dividing the first quantum circuit into a first group and a second group along the cutting line, rearranging the at least two qubits, calculates a final operation value by merging a first operation value of the first group and a second operation value of the second group in the second quantum circuit, and rearranges the at least two qubits of the second quantum circuit to be the same as the first quantum circuit.

Abstract: Disclosed is a multi-constraint qubit allocation method and a quantum apparatus using the same. The method comprises generating an interaction graph representing a quantum circuit on the basis of the number of two-qubit gates, determining edge weights between connected nodes in the interaction graph by introducing a fitting coefficient for a decay effect, searching for an isomorphic part, layout graph, between target hardware and the interaction graph by graph matching, and performing frequency matching for a layout graph by searching for frequency allocated to each location of qubits by limiting unidirectional movement on each of an x-axis and a y-axis of a hardware plane of the target hardware to a range from ?1 to +1.

Abstract: A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.

Abstract: A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.

Abstract: A device and method for determining a defective area on an optical media (disc) by counting the number of errors within ECC blocks of the data stored thereon. The defect detection is generally performed by Error Counters and Comparator circuits, for counting the number of occurrences of errors (e.g., parity errors) in an ECC block of the data and for comparing the counted number of occurrences of errors with a supplied threshold. The threshold may be preset at a maximum to distinguish between “correctable” and “uncorrectable” numbers of errors, or may be set lower to better secure the recorded data and to improve the resiliency of the media to subsequent scratches, fingerprints, etc. When the threshold is exceeded, the area is determined to be defective. A position-determining unit keeps track of the location of the ECC block under examination and flags the position of the defective area based on the position of the ECC block containing a number of errors exceeding the threshold.

Abstract: A device and method for determining a defective area on an optical media (disc) by counting the number of errors within ECC blocks of the data stored thereon. The defect detection is generally performed by Error Counters and Comparator circuits, for counting the number of occurrences of errors (e.g., parity errors) in an ECC block of the data and for comparing the counted number of occurrences of errors with a supplied threshold. The threshold may be preset at a maximum to distinguish between “correctable” and “uncorrectable” numbers of errors, or may be set lower to better secure the recorded data and to improve the resiliency of the media to subsequent scratches, fingerprints, etc. When the threshold is exceeded, the area is determined to be defective. A position-determining unit keeps track of the location of the ECC block under examination and flags the position of the defective area based on the position of the ECC block containing a number of errors exceeding the threshold.