Abstract: A bit manipulation circuit which can speedily carry out unit operations, such as repetitive data shifts and modulo-2 additions, and bit extraction and insertion, so as to facilitate the operation of a communication system involved with such unit operations while maintaining simple hardware complexity. The bit manipulation circuit is suitable for use in a programmable processor comprising a register bank for temporarily storing an operand data and performs data encoding operation based data shift modulo-2 addition, and bit extraction and insertion operation. In the circuit, a shift addition array receives the operand data, generates a plurality of shifted data being shifted from the operand data by one bit through the bit width of the operand data, carries out Mod-2 additions in parallel with respect to the operand data and at least some of the plurality of shifted data, and stores the addition result in the register bank.