Patents by Inventor Seok-Il Kim
Seok-Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961551Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo Bong Chang, Young-Il Lim, Bok-Yeon Won, Seok Jae Lee, Dong Geon Kim, Myeong Sik Ryu, In Seok Baek, Kyoung Min Kim, Sang Wook Park
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Publication number: 20240099390Abstract: An aerosol generating device includes: a housing including a hole for receiving an aerosol generating article and a guide apart from the hole; and a cover configured to move along the guide between a first position and a second position to open or close the hole, wherein the hole is open when the cover is located in the first position, and the hole is closed when the cover is located in the second position.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Applicant: KT&G CORPORATIONInventors: Dong Sung KIM, Yong Hwan KIM, Hun Il LIM, Seok Su JANG
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Patent number: 11927890Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.Type: GrantFiled: August 22, 2022Date of Patent: March 12, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Heo, Cha Won Koh, Sang Joon Hong, Hyun Woo Kim, Kyung-Won Kang, Dong-Wook Kim, Kyung Won Seo, Young Il Jang, Yong Suk Choi
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Patent number: 9128817Abstract: An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability.Type: GrantFiled: January 5, 2012Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il Kim, You-Keun Han, Sung-Ho Choi
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Patent number: 8742780Abstract: A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.Type: GrantFiled: October 29, 2010Date of Patent: June 3, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, Ho-Suk Lee, You-Keun Han, Yang-Ki Kim
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Patent number: 8576637Abstract: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.Type: GrantFiled: December 3, 2010Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Soon-Deok Jang, Seok-Il Kim, Seung-Jin Seo, You-Keun Han
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Patent number: 8547761Abstract: A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.Type: GrantFiled: October 4, 2010Date of Patent: October 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, You-Keun Han, Jung-Joon Lee
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Patent number: 8462534Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: GrantFiled: March 27, 2012Date of Patent: June 11, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, You-Keun Han, Seung-Jin Seo
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Publication number: 20120239903Abstract: An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability.Type: ApplicationFiled: January 5, 2012Publication date: September 20, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il Kim, You-Keun Han, Sung-Ho Choi
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Publication number: 20120182777Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il KIM, You-Keun HAN, Seung-Jin SEO
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Patent number: 8159853Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: GrantFiled: January 25, 2010Date of Patent: April 17, 2012Assignee: Samsung Electronis Co., Ltd.Inventors: Seok-Il Kim, You-Keun Han, Seung-Jin Seo
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Publication number: 20110176371Abstract: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.Type: ApplicationFiled: December 3, 2010Publication date: July 21, 2011Inventors: Soon-Deok Jang, Seok-Il Kim, Seung-Jin Seo, You-Keun Han
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Publication number: 20110161576Abstract: A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.Type: ApplicationFiled: October 4, 2010Publication date: June 30, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il KIM, You-Keun HAN, Jung-Joon LEE
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Patent number: 7965530Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.Type: GrantFiled: December 8, 2008Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: You-Keun Han, Seung-Jin Seo, Kwan-Yong Jin, Jung-Hwan Choi, Jong-Hoon Kim, Seok-Il Kim, Joo-Sun Choi
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Publication number: 20110115509Abstract: A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.Type: ApplicationFiled: October 29, 2010Publication date: May 19, 2011Inventors: Seok-Il Kim, Ho-Suk Lee, You-Keun Han, Yang-Ki Kim
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Patent number: 7930465Abstract: A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.Type: GrantFiled: October 21, 2005Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, Young-Man Ahn, Byung-Se So, Seung-Jin Seo
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Publication number: 20100202180Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.Type: ApplicationFiled: January 25, 2010Publication date: August 12, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Il KIM, You-Keun HAN, Seung-Jin SEO
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Publication number: 20090103374Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.Type: ApplicationFiled: December 8, 2008Publication date: April 23, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: You-Keun HAN, Seung-Jin SEO, Kwan-Yong JIN, Jung-Hwan CHOI, Jong-Hoon KIM, Seok-Il KIM, Joo-Sun CHOI
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Patent number: 7426149Abstract: A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a first signal line set comprising a plurality of first signal lines connected to the plurality of semiconductor memory devices, and a plurality of second signal line sets. Each semiconductor memory device comprises first terminals adapted to receive first signals from the first signal lines, second terminals connected to a corresponding one of the second signal line sets, a third terminal adapted to receive an enable signal during the test mode, and a signal transmitting unit adapted to output second signals to the second terminals in response to the enable signal.Type: GrantFiled: October 2, 2006Date of Patent: September 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Il Kim, You-Keun Han, Hoe-Ju Chung, Young-Man Ahn
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Patent number: 7330008Abstract: An apparatus for detecting a vehicle seat position is disclosed. The apparatus includes a hall sensor for detecting a target position according to a flux variation; a first power-supply unit for activating the hall sensor in an active period of a received drive-voltage pulse; and a second power-supply unit for providing an auxiliary power-supply signal to activate the hall sensor in an inactive period of the drive-voltage pulse. Therefore, the apparatus can effectively address two-pin hall sensor's problems caused by hysteresis characteristics.Type: GrantFiled: March 9, 2006Date of Patent: February 12, 2008Assignee: Tyco Electronics AMP Korea Ltd.Inventors: Cheol-Seob Lee, Seok-Il Kim, Dug-Su Yang, You-Sik Choi