Abstract: A semiconductor device includes: a substrate; an active region in the substrate; a device isolation layer defining the active region; a gate structure in the substrate and extending across the active region in a first horizontal direction; bit line structures on the substrate, extending in a second horizontal direction intersecting the first horizontal direction, and crossing the gate structure; and a contact structure between the bit line structures, wherein the contact structure includes: a first contact plug in contact with the active region; a second contact plug on the first contact plug; and a third contact plug on the second contact plug, and wherein a first vertical central axis of the active region, a second vertical central axis of the first contact plug, and a third vertical central axis of the third contact plug are offset from each other in a cross-sectional view.

Abstract: A method of manufacturing an integrated circuit device includes providing a substrate including a cell array area and a peripheral circuit area; forming a conductive layer in the cell array area and the peripheral circuit area; forming a capping insulating layer on the conductive layer; forming, in the cell array area, a direct contact and a bit line by using the capping insulating layer as a first etching mask; forming a spacer structure on side walls of the direct contact and on side walls of the bit line; forming a buried contact that is between the direct contact and the bit line and a first side wall of the side walls of the bit line; forming an insulating spacer on the cell array area and the peripheral circuit area; and forming, in the peripheral circuit area, a gate structure by using the insulating spacer as a second etching mask.

Abstract: A semiconductor device includes a substrate that includes an active region including first and second impurity regions, the substrate further including a contact hole that overlaps an upper surface of the first impurity region; a gate structure in the substrate and intersecting the active region; a bit line structure intersecting the gate structure, the bit line structure including a bit line contact and a bit line on the bit line contact; a spacer structure including an internal spacer on a side surface of the bit line structure and an external spacer on the internal spacer; and a contact plug in contact with a first side surface of the external spacer and electrically connected to the second impurity region. The internal spacer includes a first spacer in contact with a second side surface of the external spacer. The first spacer includes a different material from the external spacer.

Abstract: The present inventive concepts relate to semiconductor devices and methods for fabricating the same, and a semiconductor device according to some example embodiments includes: a substrate including an active region defined by a device isolation layer; a word line that crosses and overlaps the active region; a bit line crossing the active region in a direction different from the word line; a direct contact that connects the active region and the bit line and includes a metallic material; a buried contact connected to the active region; and a bit line spacer between the bit line and the buried contact, wherein a width of the direct contact is different from that of the bit line, and the bit line spacer is on an upper surface of the direct contact.

Abstract: Disclosed is a semiconductor device comprising an active pattern on a substrate and surrounded by a device isolation pattern, a word line that extends in a first direction and is on the active pattern and the device isolation pattern in a first direction parallel to a bottom surface of the substrate, a bit line that extends on the active pattern in a second direction intersecting the first direction, a storage node contact on the active pattern, a landing pad that includes a lower landing pad and an upper landing pad that are sequentially provided on the storage node contact with an interface therebetween, and a fence pattern on the word line and a lateral surface of the landing pad. A top surface of the fence pattern is has a height higher than a height a top surface of the lower landing pad.

Abstract: A semiconductor device may include a device isolation part on a substrate, the device isolation part defining a first active portion and a second active portion, with a center portion of the first active portion adjacent in a first direction to an edge portion of the second active portion, A first impurity region may be in the center portion of the first active portion, and a second impurity region may be in the edge portion of the second active portion. A first bit line may be in direct contact with the first impurity region and may extend across the substrate in a second direction that intersects the first direction. A storage node contact may be in contact with the second impurity region, with an upper sidewall and a lower sidewall of the storage node contact on a common side of the storage node contact not vertically aligned with each other.

Abstract: The present disclosure provides semiconductor devices including a bit line. In some embodiments, a semiconductor device includes a substrate including a plurality of active regions defined by device isolation layers, a plurality of bit lines extending in a first horizontal direction on the substrate, a bit line contact between a first active region of the plurality of active regions and a first bit line of the plurality of bit lines on the first active region, and an active pad on a second active region of the plurality of active regions adjacent to the first active region. The bit line contact includes a first contact layer and a second contact layer on the first contact layer. The active pad is disposed to face the bit line contact.

Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines.

Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines.