Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

Abstract: A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.

Abstract: A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.

Abstract: A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

Abstract: A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

Abstract: The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.

Abstract: A method of operating a data storage device configured to allow a plurality of non-volatile memory devices, including a first non-volatile memory device and second non-volatile memory devices, to lead control of power consumption. The method includes receiving, by each of the second non-volatile memory devices, a state signal indicating operation or non-operation of the first non-volatile memory device and determining, by each of the second non-volatile memory device, whether to operate based on the state signal.

Abstract: A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

Abstract: A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Abstract: A non-volatile memory system includes a memory controller, where the memory controller includes a first region including a first memory that stores compressed code, and a second region including a second memory that stores decompressed code. Power supplied to the first region and the second region is controlled according to an operation mode of the non-volatile memory system.

Abstract: A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Abstract: A method of operating a data storage device configured to allow a plurality of non-volatile memory devices, including a first non-volatile memory device and second non-volatile memory devices, to lead control of power consumption. The method includes receiving, by each of the second non-volatile memory devices, a state signal indicating operation or non-operation of the first non-volatile memory device and determining, by each of the second non-volatile memory device, whether to operate based on the state signal.

Abstract: The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.

Abstract: A data storage device includes a first scale-out controller configured to control a first non-volatile memory and a first volatile memory, a second scale-out controller configured to control a second non-volatile memory and a second volatile memory, and a controller configured to set a first memory management policy for the first non-volatile memory to be different from a second memory management policy for the second non-volatile memory.

Abstract: A non-volatile memory and a method of controlling an erase operation of the non-volatile memory using a controller are provided. The method of controlling the erase operation includes beginning performance of the erase operation, monitoring a next command to be performed in the non-volatile memory while performing the erase operation, determining an erase status, and continuing, suspending or canceling the erase operation based on the determination result of the erase status.

Abstract: An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.

Abstract: Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data.

Abstract: A non-volatile memory system includes a memory controller, where the memory controller includes a first region including a first memory that stores compressed code, and a second region including a second memory that stores decompressed code. Power supplied to the first region and the second region is controlled according to an operation mode of the non-volatile memory system.

Abstract: A non-volatile memory and a method of controlling an erase operation of the non-volatile memory using a controller are provided. The method of controlling the erase operation includes beginning performance of the erase operation, monitoring a next command to be performed in the non-volatile memory while performing the erase operation, determining an erase status, and continuing, suspending or canceling the erase operation based on the determination result of the erase status.

Abstract: A method of programming a memory device includes generating a row selection signal according to a command type of a command received from a memory controller, loading data to page buffers corresponding to bit lines assigned by the column selection signal, and programming memory cells connected to a word line assigned by the row selection signal based on the data loaded to the page buffers. The column selection signal being generated to selectively jump a portion of the page buffers corresponding to the bit lines according to the command type.