Abstract: Providing lower-overhead management of dataflow execution of loop instructions by out-of-order processors (OOPs), and related circuits, methods, and computer-readable media are disclosed. In one aspect, a reservation station circuit including multiple reservation station segments, each storing a loop instruction of a computer program loop is provided. Each reservation station segment also stores an instruction execution credit indicator indicative of whether the corresponding loop instruction may be provided for dataflow execution. The reservation station circuit further includes a dataflow monitor providing an entry for each loop instruction, each entry comprising a consumer count indicator and a reservation station (RS) tag count indicator. The dataflow monitor is configured to determine whether all consumer instructions of a loop instruction have executed based on the consumer count indicator and the RS tag count indicator for the loop instruction.

Abstract: Enforcing loop-carried dependency (LCD) during dataflow execution of loop instructions by out-of-order processors (OOPs), and related circuits, methods, and computer-readable media, is disclosed. In one aspect, a reservation station circuit is provided, comprising one or more reservation station segments configured to store a consumer loop instruction. Each reservation station segment also includes an operand buffer for each operand of the consumer loop instruction, the operand buffer indicating a producer loop instruction and an LCD distance between the producer loop instruction and the consumer loop instruction. Each reservation station segment receives an execution result of the producer loop instruction, and a loop iteration indicator that indicates a current loop iteration for the producer loop instruction.

Abstract: Managing dataflow execution of loop instructions by out-of-order processors (OOPs), and related circuits, methods, and computer-readable media are disclosed. In one aspect, a reservation station circuit is provided. The reservation station circuit includes multiple reservation station segments, each storing a loop instruction of a loop of a computer program. Each reservation station segment also stores an instruction execution credit indicating whether the corresponding loop instruction may be provided for dataflow execution. The reservation station circuit further includes a dataflow monitor that distributes an initial instruction execution credit to each reservation station segment. As each loop iteration is executed, each reservation station segment determines whether the instruction execution credit indicates that the loop instruction for the reservation station segment may be provided for dataflow execution.

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract: The various embodiments provide circuitry and methods for packing Log Likelihood Ratio (“LLR”) values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.

Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

Abstract: The various embodiments provide circuitry and methods for packing Log Likelihood Ratio (“LLR”) values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.