Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.

Abstract: An apparatus and method for processing a primitive in a three-dimensional (3D) graphics rendering system is provided. The primitive processing apparatus may discard a primitive or store the primitive in a memory, depending on whether a sampling point overlapping the primitive is present among sampling points in a pixel area.

Abstract: A rendering method includes determining, at a geometry processor, if a previous draw command from among previous draw commands is identical to a current draw command; in response to the previous draw command being identical to the current draw command, selecting a primitive list indicating a result of geometry processing performed on the previous draw command; and performing pixel processing using the primitive list.

Abstract: A rendering system and method. The rendering system may perform rendering using a rendering context stored in an internal memory. When a rendering context to be used is not available in the internal memory, the rendering system may load the rendering context to be used from an external memory into the internal memory. When an insufficient amount of storage space is available in the internal memory, storage space may be secured by selectively deleting a rendering context from the internal memory, and a requested rendering context stored in the external memory may be loaded into the internal memory.

Abstract: Provided is a method and apparatus for ray tracing. A traversal unit to process an input ray to be input among a plurality of traversal units may be determined based on age of each of the plurality of traversal units. Age of the determined traversal unit may be determined based on age of each of rays that are processed by the traversal unit.

Abstract: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.

Abstract: An apparatus and method for tile binning with respect to a Bezier curve. The apparatus may include a curve identification unit to identify a Bezier curve included in input data, a bounding box generation unit to generate a plurality of bounding boxes corresponding to the Bezier curve, and a tile binning unit to perform tile binning with respect to the Bezier curve based on the plurality of bounding boxes.

Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.

Abstract: Methods and apparatuses of converting a program, which may enhance an execution speed of a computer program, are provided. The method may include receiving a program, detecting at least one loop statement including at least one branch statement within the program, determining whether the loop statement may be split into at one or more sub-loop statements which perform the same function as a function of the loop statement and from which the branch statement has been removed, splitting the loop statement into the sub-loop statements and removing the branch statement included in the loop statement if it is determined that the loop statement may be split as a result of the determination, and outputting a result of removing the branch statement.

Abstract: A method for tile-based rendering may include verifying a size of a memory available in an apparatus for rendering, and determining a number of buffers required for performing a rendering based on graphics data input, and may further include determining a size of a tile to be used for performing the rendering based on the determined number of buffers and the size of the memory available.

Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.

Abstract: Disclosed is a method and apparatus for performing tile-based rendering. A sequence of tiles to be processed may be determined based on a locality among the tiles. A tile dispatch unit selects a subsequent tile to be dispatched, based on the determined sequence.

Abstract: A method for processing a three-dimensional (3D) image of a ray tracing scheme may be performed by an image processing apparatus by verifying whether local index information matching intersection point information of a ray is present within a prefetch table when intersection point information is received, and by transferring, to a shader, rendering information stored in a local memory based on the local index information, when the local index information matching the intersection point information is present.

Abstract: Provided is a rendering method and apparatuses for rendering image data. The rendering method includes generating a primitive list by performing geometry processing on a current tile to be rendered; determining whether the current tile is identical to a previous tile from among tiles included in a previously rendered frame; and in response to the previous tile being identical to the current tile, generating an image of the current tile by re-using an image of the previous tile.

Abstract: An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.

Abstract: A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.

Abstract: A method and apparatus for configuring dynamic data are provided. A compilation apparatus may select a data format showing an optimum performance when a binary code is executed, from among a plurality of data formats supported by an execution apparatus used to execute a binary code, and may generate a binary code that uses the selected data format. The execution apparatus may execute a binary code provided by the compilation apparatus.

Abstract: A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.

Abstract: A method and apparatus for providing shared caches. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, at least one bit may overlap tag bits and set index bits among bits of a memory address.