Patents by Inventor Seol Min Yi

Seol Min Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240420752
    Abstract: A semiconductor system includes a controller outputting a clock, a chip selection signal, a command address, and data, and a semiconductor device performing an auto-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the auto-refresh operation, correcting an error of internal data stored therein by performing a read-modify-write operation instead of the auto-refresh operation when the auto-refresh operation is performed a first set number of times and storing the corrected internal data, performing a self-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the self-refresh operation, and correcting an error of the internal data stored therein by performing a read-modify-write operation instead of the self-refresh operation when the self-refresh operation is performed a second set number of times and to store the corrected internal
    Type: Application
    Filed: October 17, 2023
    Publication date: December 19, 2024
    Applicant: SK hynix Inc.
    Inventors: Woongrae KIM, Seol Min YI, Kyoung Chul JANG
  • Patent number: 9224619
    Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seol-Min Yi, Dae-Hyun Moon, Joon-Seok Moon, Se-Keun Park, Hyeoung-Won Seo
  • Publication number: 20150221742
    Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.
    Type: Application
    Filed: September 30, 2014
    Publication date: August 6, 2015
    Inventors: Seol-Min YI, Dae-Hyun MOON, Joon-Seok MOON, Se-Keun PARK, Hyeoung-Won SEO
  • Patent number: 8216635
    Abstract: Disclosed are a method of forming metal wiring and metal wiring formed using the same. The method includes printing wiring using an ink composition including metallic nanoparticles and dispersants maintaining dispersion of the metallic nanoparticles, performing a first firing process of firing the wiring under vacuum or in an inert atmosphere to suppress grain growth, and performing a second firing process of firing the wiring with the vacuum or inert atmosphere released, to accelerate grain growth. The method of forming metal wiring induces abnormal grain growth by rapidly removing dispersants, capable of inducing the growth of metallic nanoparticles, at a temperature at which the growth force of the metallic nanoparticles is high, in the process of firing the metallic nanoparticles. Accordingly, the metal wiring has a coarse-grained structure containing metallic particles with a large average particle size, and the electrical and mechanical characteristics thereof can be enhanced.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: July 10, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ah Song, Young Chang Joo, Ji Hoon Lee, Seol Min Yi, Jae Woo Joung, Sung Il Oh, Tae Hoon Kim, In Young Kim
  • Publication number: 20100196681
    Abstract: Disclosed are a method of forming metal wiring and metal wiring formed using the same. The method includes printing wiring using an ink composition including metallic nanoparticles and dispersants maintaining dispersion of the metallic nanoparticles, performing a first firing process of firing the wiring under vacuum or in an inert atmosphere to suppress grain growth, and performing a second firing process of firing the wiring with the vacuum or inert atmosphere released, to accelerate grain growth. The method of forming metal wiring induces abnormal grain growth by rapidly removing dispersants, capable of inducing the growth of metallic nanoparticles, at a temperature at which the growth force of the metallic nanoparticles is high, in the process of firing the metallic nanoparticles. Accordingly, the metal wiring has a coarse-grained structure containing metallic particles with a large average particle size, and the electrical and mechanical characteristics thereof can be enhanced.
    Type: Application
    Filed: July 15, 2009
    Publication date: August 5, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ah SONG, Young Chang Joo, Ji Hoon Lee, Seol Min Yi, Jae Woo Joung, Sung Il Oh, Tae Hoon Kim, In Young Kim