Patents by Inventor Seong-Yeong Lee

Seong-Yeong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967267
    Abstract: Provided is a display device including a display panel, an optical sensor, a timing controller, a scan driver, a data driver, and an image controller. The timing controller controls an image refresh rate of the display panel based on a refresh rate control signal. Thus, the display device provides improved visibility.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: April 23, 2024
    Assignees: Samsung Display Co., Ltd., UNIST (Ulsan National Institute Of Science and Technology)
    Inventors: Hyo Sun Kim, Oh Sang Kwon, Seong Gyu Choe, Chang Yeong Han, Min Kyung Kim, You Ra Kim, Eun Jung Lee, Hyung Suk Hwang
  • Patent number: 8294151
    Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Wook Kim, Joo-Ae Youn, Seong-Yeong Lee
  • Patent number: 7662651
    Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Wook Kim, Joo-Ae Youn, Seong-Yeong Lee