Abstract: In some embodiments of the disclosed technology, a memory controller may include a data strobe signal (DQS) calibration circuit configured to calibrate timing of a data strobe signal (DQS) for a plurality of memory dies by performing N unit DQS calibration operations, wherein N is a natural number, wherein performing the N unit DQS calibration operations includes: performing M unit DQS calibration operations in a normal mode on the plurality of memory dies, wherein M is a natural number smaller than N; upon failure of calibration during the M unit DQS calibration operations in the normal mode, determining a representative memory die of the plurality of memory dies that causes the failure of calibration; and performing N?M unit DQS calibration operations in a conditional mode on the plurality of memory dies by varying parameters associated with the representative memory die of the plurality of memory dies.

Abstract: A storage device of the present disclosure includes a memory device including a plurality of pages, and a memory controller configured to determine whether a data shift error occurs in read data read from a selected page among the plurality of pages based on a number of bits having a first bit-value and a number of bits having a second bit-value among a plurality of bits included in the read data, and shift the read data when the data shift error occurs.