Abstract: A multilayer electronic component according to another exemplary embodiment of the present disclosure may suppress occurrence of a short circuit between the internal electrodes, lower capacitance or reduced breakdown voltage by controlling an area fraction of a region of a capacitance formation portion, in which a range of brightness intensity is 110% or more and 126% or less compared to an average value of brightness intensity of a cover portion.

Abstract: A multilayer electronic component according to an exemplary embodiment of the present disclosure may control connectivity of an end of an internal electrode, thereby suppressing occurrence of a short circuit between the internal electrodes, reduced capacitance or lower breakdown voltage.

Abstract: A multilayer electronic component includes: a body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with the dielectric layers in a first direction, wherein when a space where the plurality of internal electrodes overlap each other in the first direction is defined as a capacitance forming portion, the plurality of internal electrodes include internal electrodes that are curved at end portions thereof in the capacitance forming portion and internal electrodes that are flat in the capacitance forming portion, and in a cross section of the body in the first and second directions.

Abstract: A multilayer electronic component according to an exemplary embodiment of the present disclosure may control connectivity of an end of an internal electrode, thereby suppressing occurrence of a short circuit between the internal electrodes, reduced capacitance or lower breakdown voltage. The internal electrode may include a plurality of conductor portions and a plurality of cut-off portions.

Abstract: There is provided a multilayer electronic component in which a short circuit between the internal electrodes, a decrease in capacitance, a decrease in breakdown voltage, and the like, may be suppressed by controlling an area fraction occupied by a region in which an intensity of brightness in a capacitance formation portion is 110% or more and 126% or less of an average value of an intensity of brightness of a cover portion.

Abstract: A multilayer electronic component includes: a body including internal electrodes alternately disposed with dielectric layers in a first direction, wherein when a region in which the internal electrodes overlap each other in the first direction is a capacitance forming portion, the internal electrodes include internal electrodes that are curved at end portions thereof in the capacitance forming portion and internal electrodes that are flat in the capacitance forming portion, and in a cross-section of the body in the first and second directions, (F1+F2)/D1×100 is 35 or less, where F1 is a maximum distance from an uppermost internal electrode to an uppermost flat internal electrode in the first direction, F2 is a maximum distance from a lowermost internal electrode to a lowermost flat internal electrode in the first direction, and D1 is a size of the capacitance forming portion in the first direction at the center thereof in the second direction.

Abstract: Provided are a multilayer ceramic electronic component and a method for manufacturing the same, the multilayer ceramic electronic component including a ceramic body including a dielectric layer and an internal electrode, and an external electrode formed on an outer side of the ceramic body and electrically connected to the internal electrode, wherein the internal electrode includes a conductive metal and an additive, and the number of particles of the additive disposed per ?m2 of the internal electrode is in the range of 7 to 21, both inclusive.

Abstract: A capacitor includes a body including dielectric layers and internal electrodes; and external electrodes disposed on the body. The capacitor includes Sn, the Sn having an alpha particle emission rate equal to or less than 0.02 cph/cm2.

Abstract: Provided are a multilayer ceramic electronic component and a method for manufacturing the same, the multilayer ceramic electronic component including a ceramic body including a dielectric layer and an internal electrode, and an external electrode formed on an outer side of the ceramic body and electrically connected to the internal electrode, wherein the internal electrode includes a conductive metal and an additive, and the number of particles of the additive disposed per ?m2 of the internal electrode is in the range of 7 to 21, both inclusive.

Abstract: A capacitor includes a body including dielectric layers and internal electrodes; and external electrodes disposed on the body. The capacitor includes Sn, the Sn having an alpha particle emission rate equal to or less than 0.02 cph/cm2.

Abstract: A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal.

Abstract: Disclosed herein is substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided.

Abstract: Disclosed herein are a mask for bumping solder balls on a circuit board and a solder ball bumping method using the same. The mask includes: a plurality of openings providing spaces into which the solder balls are inserted to thereby be seated on solder pads; and trenches providing introduction spaces for spreading a flux to portions at which the solder balls are seated on the solder pads and extended from at least one side of circumferences of the openings.

Abstract: Disclosed is a substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided.

Abstract: A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal.

Abstract: There is provided a method of manufacturing a substrate for flip chip, and a substrate for flip chip manufactured using the same. The method includes providing a base substrate including at least one conductive pad, forming a solder resist layer on the base substrate, the solder resist layer including a first opening exposing the conductive pad, forming a dry film on the solder resist layer, the dry film including a second opening connected with the first opening, forming a metal post in the first opening and a part of the second opening, filling the second opening above the metal post with solder paste, forming a solder cap by performing a reflow process on the filled solder paste, planarizing a surface of the solder cap, and removing the dry film. Accordingly, fine pitches and improve reliability can be achieved.

Abstract: There is provided a package substrate capable of controlling the degree of warpage thereof by improving the composition and formation of a post terminal and a method of fabricating the same. The package substrate includes a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a separation barrier layer provided on the conductive pad inside the opening and formed to be higher than the upper surface of the insulating layer along the side walls thereof; a post terminal provided on the separation barrier layer; and a solder bump provided on the post terminal.

Abstract: A squeegee module. The squeegee module of the present invention includes a rotary unit rotated in opposite directions, support rods mounted to the rotary unit on opposite sides of the center of the rotary unit, a squeegee holder connected to ends of the support rods, and a squeegee blade mounted to the squeegee holder, wherein the squeegee holder moves upwards and downwards in cooperation with rotation of the rotary unit, thus controlling the inclination angle of the squeegee blade.

Abstract: There is provided a package substrate capable of controlling the degree of warpage thereof by improving the composition and formation of a post terminal and a method of fabricating the same. The package substrate includes a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a separation barrier layer provided on the conductive pad inside the opening and formed to be higher than the upper surface of the insulating layer along the side walls thereof; a post terminal provided on the separation barrier layer; and a solder bump provided on the post terminal.

Abstract: There is provided a package substrate allowing for enhanced reliability by improving the structure of a solder bump and a method of fabricating the same. The package substrate includes: a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a post terminal provided on the conductive pad inside the opening; and a solder bump provided on the post terminal and having an angle between a bottom surface and a side surface thereof ranging from 80° to 120°.