Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Abstract: A transmission line RF applicator apparatus and method for coupling RF power to a plasma in a plasma chamber. The apparatus comprises two conductors, one of which has a plurality of apertures. In one aspect, apertures in different portions of the conductor have different sizes, spacing or orientations. In another aspect, adjacent apertures at successive longitudinal positions are offset along the transverse dimension. In another aspect, the apparatus comprises an inner conductor and one or two outer conductors. The main portion of each of the one or two outer conductors includes a plurality of apertures that extend between an inner surface and an outer surface of the outer conductor.

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Abstract: An apparatus for introducing gas into a processing chamber comprising one or more gas distribution tubes having gas-injection holes which may be larger in size, greater in number, and/or spaced closer together at sections of the gas introduction tubes where greater gas conductance through the gas-injection holes is desired. An outside tube having larger gas-injection holes may surround each gas distribution tube. The gas distribution tubes may be fluidically connected to a vacuum foreline to facilitate removal of gas from the gas distribution tube at the end of a process cycle.

Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, without the need of a subsequent anneal treatment.

Abstract: Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.

Abstract: The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer.

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. An IGZO layer is formed above the substrate. The IGZO layer is annealed in an environment consisting essentially of nitrogen gas.

Abstract: A transmission line RF applicator apparatus and method for coupling RF power to a plasma in a plasma chamber. The apparatus comprises two conductors, one of which has a plurality of apertures. In one aspect, apertures in different portions of the conductor have different sizes, spacing or orientations. In another aspect, adjacent apertures at successive longitudinal positions are offset along the transverse dimension. In another aspect, the apparatus comprises an inner conductor and one or two outer conductors. The main portion of each of the one or two outer conductors includes a plurality of apertures that extend between an inner surface and an outer surface of the outer conductor.

Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, without the need of a subsequent anneal treatment.

Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The third target includes a compound of indium oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, when deposited at room temperature, without the need of a subsequent anneal treatment.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO) with intra-layer variations and methods for forming such IGZO. At least a portion of a substrate is positioned in a processing chamber. A first sub-layer of an IGZO layer is formed above the at least a portion of the substrate while the at least a portion of the substrate is in the processing chamber. The first sub-layer of the IGZO layer is formed using a first set of processing conditions. A second sub-layer of the IGZO layer is formed above the first sub-layer of the IGZO layer while the at least a portion of the substrate is in the processing chamber. The second sub-layer of the IGZO layer is formed using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A layer is formed above the substrate using a PVD process. The layer includes indium, gallium, zinc, or a combination thereof. The PVD process is performed in a gaseous environment having a pressure of between about 1 mT and about 5 mT and including between about 20% and about 100% oxygen gas. The PVD process may be performed at a processing temperature between about 25° C. and about 400° C. The duty cycle of the PVD process may be between about 70% and about 100%.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. An IGZO layer is formed above the substrate. The IGZO layer is annealed in an environment consisting essentially of nitrogen gas.

Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is positioned relative to at least one target. The at least one target includes indium, gallium, zinc, or a combination thereof. A substantially constant voltage is provided across the substrate and the at least one target to cause a plasma species to impact the at least one target. The impacting of the plasma species on the at least one target causes material to be ejected from the at least one target to form an IGZO layer above the substrate.

Abstract: A transmission line RF applicator apparatus and method for coupling RF power to a plasma in a plasma chamber. The apparatus comprises an inner conductor and one or two outer conductors. The main portion of each of the one or two outer conductors includes a plurality of apertures that extend between an inner surface and an outer surface of the outer conductor.

Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate in a processing chamber, maintaining the processing chamber at a temperature below 400° C., flowing a reactant gas comprising either a silicon hydride or a silicon halide and an oxidizing precursor into the process chamber, applying a microwave power to create a microwave plasma from the reactant gas, and depositing a silicon oxide layer on at least a portion of the exposed surface of a substrate.

Abstract: A method of processing a substrate in a processing chamber is provided. The method generally includes applying a microwave power to an antenna coupled to a microwave source disposed within the processing chamber, wherein the microwave source is disposed relatively above a gas feeding source configured to provide a gas distribution coverage covering substantially an entire surface of the substrate, and exposing the substrate to a microwave plasma generated from a processing gas provided by the gas feeding source to deposit a silicon-containing layer on the substrate at a temperature lower than about 200 degrees Celsius, the microwave plasma using a microwave power having a power density of about 500 milliWatts/cm2 to about 5,000 milliWatts/cm2 at a frequency of about 1 GHz to about 10 GHz.