Abstract: The present technology may include an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data, and a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and to share substantially the same signal path in generating the first delay data and in generating the second delay data.

Abstract: A display device includes a display panel including pixels in one pixel column and a gate driver for sequentially providing scan signals to the pixels. Each of the pixels includes a light emitting element, a first transistor for controlling a current amount of driving current flowing through the light emitting element and a second transistor for transferring a data signal to a gate electrode of the first transistor in response to a corresponding scan signal among the scan signals. A first pixel among the pixels is electrically connected to a first data line, and a second pixel adjacent to the first pixel among the pixels is electrically connected to a second data line different from the first data line. A second scan signal provided to the second pixel partially overlaps with a first scan signal provided to the first pixel.

Abstract: The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

Abstract: The present invention provides an optical filter for its use. In the present invention, it is possible to provide an optical filter that effectively blocks ultraviolet ray and infrared ray and exhibits high transmittance in visible light. Furthermore, it is possible to provide an optical filter where the transmission characteristics are stably maintained even when an incident angle is changed. Moreover, it is possible to provide an optical filter that does not exhibit problems such as ripple, petal flare, and curl.

Abstract: The present invention provides an optical filter for its use. In the present invention, it is possible to provide an optical filter that effectively blocks ultraviolet ray and infrared ray and exhibits high transmittance in visible light. Furthermore, it is possible to provide an optical filter where the transmission characteristics are stably maintained even when an incident angle is changed. Moreover, it is possible to provide an optical filter that does not exhibit problems such as ripple or petal flare.

Abstract: The provided is an optical filter for its use. In the present invention, it is possible to provide an optical filter that effectively blocks ultraviolet ray and infrared ray and exhibits high transmittance in visible light. Furthermore, it is possible to provide an optical filter where the transmission characteristics are stably maintained even when an incident angle is changed. Moreover, it is possible to provide an optical filter that does not exhibit problems such as ripple and petal flare, and thus to provide the optical filter with excellent durability.

Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

Abstract: The present technology may include an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data, and a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and to share substantially the same signal path in generating the first delay data and in generating the second delay data.

Abstract: The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.