Abstract: The present invention relates to a composition for forming a composite polymer film, a method for preparing the composition for forming a composite polymer film, a composite polymer film and a method for preparing the composite polymer film. The composition for forming a composite polymer film comprises: a fluorine-based polymer solution comprising a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the fluorine-based polymer solution. The method for preparing the composition for forming a composite polymer film comprises the steps of: preparing a fluorine-based polymer solution comprising a fluorine-based polymer; and dispersing polyvinylidene fluoride nanoparticles in the fluorine-based polymer solution. The composite polymer film comprises: a polymer matrix formed from a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the polymer matrix.

Abstract: This application relates to a composition for preventing, treating, and improving skeletal muscle atrophy, the composition including an organoselenium compound. The composition recovered the thickness of muscle fiber reduced by dexamethasone treatment. In addition, the treatment of mice in a muscle loss model showed that the composition had an effect of reducing damaged muscle and of restoring muscle mass. Therefore, it is expected that the composition can be effectively used for the treatment, prevention, or improvement of muscle atrophy.

Abstract: A Processing-in-Memory (PIM) computing system and a memory controller provide improved memory traffic efficiency and improved PIM operation efficiency by increasing a burst length of a PIM operation relative to a general memory request. In embodiments, the increased burst length allows the PIM operation to be performed in units of pages, wherein a page is management unit of a memory used in the PIM operation.

Abstract: A Processing-In-Memory (PIM) computing system and a PIM computation offloading method thereof perform PIM computation offloading using a DMA engine. The DMA engine is configured to process a transaction by respectively performing descriptor requests and PIM requests for one or more descriptors stored in a memory, in response to a memory request of a CPU. The memory includes a PIM unit and a memory array, which memory array may be a DRAM. In response to the PIM requests, the PIM unit performs PIM operations using information included in data provided to the DMA engine in response to the descriptor requests.

Abstract: This application relates to a composition for preventing, treating, and improving skeletal muscle atrophy, the composition including an organoselenium compound. The composition recovered the thickness of muscle fiber reduced by dexamethasone treatment. In addition, the treatment of mice in a muscle loss model showed that the composition had an effect of reducing damaged muscle and of restoring muscle mass. Therefore, it is expected that the composition can be effectively used for the treatment, prevention, or improvement of muscle atrophy.

Abstract: Disclosed is a memory device including a plurality of memory banks, each of which performs an operation based on first operand data including pieces of first unit data and second operand data including pieces of second unit data and a processing in-memory interface unit (PIM IU) that delivers signals for an operation request to the plurality of memory banks. Each of the plurality of memory banks includes a memory cell array configured to store one of the pieces of first unit data and a PIM engine that reads the one of the pieces of first unit data from the memory cell array, reads the pieces of second unit data broadcast to the plurality of memory banks, and generates an operation result by performing an operation based on the one of the pieces of first unit data and the pieces of second unit data.

Abstract: A semiconductor device may include a memory controller, which may include a request queue storing requests. Requests include a memory request including a read request to a memory device or a write request to the memory device, and a process in memory (PIM) request requesting a processing operation in the memory device. The memory controller may also include a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue, a command queue storing a memory command and a PIM command output from the command generator, and a command scheduler configured to control output order, output timing, or both of a memory command and a PIM command stored in the command queue.

Abstract: A semiconductor device may include a memory controller, which may include a request queue storing requests. Requests include a memory request including a read request to a memory device or a write request to the memory device, and a process in memory (PIM) request requesting a processing operation in the memory device. The memory controller may also include a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue, a command queue storing a memory command and a PIM command output from the command generator, and a command scheduler configured to control output order, output timing, or both of a memory command and a PIM command stored in the command queue.

Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.

Abstract: A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.

Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.

Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.

Abstract: A method for extending the lifetime of a resistive change memory includes generating data and hash candidates by shuffling bit positions of write data with the hash candidates in response to a write request for the resistive change memory, calculating Hamming distances of the generated data and hash candidates from stored data and a stored hash, matching stuck data at a predetermined bit in the resistive change memory with the generated data and hash candidates when the stuck data is at the predetermined bit, and excluding mismatched data and hash candidates that are mismatched with the stuck data among the generated data and hash candidates, finding a data and hash candidate with the shortest Hamming distance among the matched data and hash candidates, and choosing the found data and hash candidate as an encoded data and hash, and storing the encoded data and hash in the resistive change memory.

Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.

Abstract: Disclosed are a virtual memory management apparatus for avoiding error cells in a main memory and a method thereof. That is, according to the present invention, it is possible to prevent a data loss or malfunction from occurring by allocating and releasing a stack frame in a way a block including the error cells to be located between the stack frames in case of a stack region, processing the block including the error cells to be in an allocated state in a heap region memory management data structure in case of a heap region, allocating the pages including error cells to programs not used frequently via profile in case of code memory, and allocating physical memory page including the error cells to unused space of last page in case of file-mapped memory.

Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.

Abstract: A method for extending the lifetime of a resistive change memory includes generating data and hash candidates by shuffling bit positions of write data with the hash candidates in response to a write request for the resistive change memory, calculating Hamming distances of the generated data and hash candidates from stored data and a stored hash, matching stuck data at a predetermined bit in the resistive change memory with the generated data and hash candidates when the stuck data is at the predetermined bit, and excluding mismatched data and hash candidates that are mismatched with the stuck data among the generated data and hash candidates, finding a data and hash candidate with the shortest Hamming distance among the matched data and hash candidates, and choosing the found data and hash candidate as an encoded data and hash, and storing the encoded data and hash in the resistive change memory.

Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.

Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.

Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.