Abstract: A method for controlling driving of a hybrid electric vehicle includes collecting driving data while the hybrid electric vehicle is driven, determining whether the hybrid electric vehicle enters a first mode corresponding to emergency driving of the hybrid electric vehicle or a second mode corresponding to control in preparation for the emergency driving, and controlling the hybrid electric vehicle in accordance with a mode that the hybrid electric vehicle enters among the first mode and the second mode.

Abstract: A memory system is provided to include a memory device and a memory controller. The memory controller is configured to set, for a first memory die, a state check memory block that is used to check a state of data stored in memory blocks included in the first memory die, and the memory controller is further configured to manage, for each of a plurality of temperature periods that are predetermined, (1) a state check page corresponding to a temperature period and included in the state check memory block and (2) a program memory block list indicating information on certain memory blocks programmed at a time that a temperature of the memory system falls within the temperature period.

Abstract: A controller for controlling an operation of a semiconductor memory device includes an error correction block and a block manager. The error correction block may perform an error correction operation on read data received from the semiconductor memory device. The block manager may analyze a result of the error correction operation and selectively perform defect processing on a target memory block in which the read data is stored, based on a number of error correction units in which an error correction failure has occurred, among a plurality of error correction units included in the read data.

Abstract: A controller for controlling an operation of a semiconductor memory device includes an error correction block and a block manager. The error correction block may perform an error correction operation on read data received from the semiconductor memory device. The block manager may analyze a result of the error correction operation and selectively perform defect processing on a target memory block in which the read data is stored, based on a number of error correction units in which an error correction failure has occurred, among a plurality of error correction units included in the read data.

Abstract: A 500 Mbps transmission apparatus is provided. The apparatus uses a 2P line which is capable of providing a 500 megabits-per-second service via a 2P UTP cable by adding a sub-layer which serializes and de-serializes symbols which have rates matched with each other and are synchronized, while maintaining a 1000BASE-T unique hierarchical architecture.

Abstract: A 500 Mbps transmission apparatus is provided. The apparatus uses a 2P line which is capable of providing a 500 megabits-per-second service via a 2P UTP cable by adding a sub-layer which serializes and de-serializes symbols which have rates matched with each other and are synchronized, while maintaining a 1000BASE-T unique hierarchical architecture.