Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: Provided is a method of operating a magnetic memory system. The method of operating the magnetic memory system includes: preparing a plurality of magnetic memory cells; classifying the magnetic memory cells into a plurality of magnetic memory cell groups by using program current values of the magnetic memory cells; constructing a magnetic memory system by hierarchizing the magnetic memory cell groups; and primarily performing programming by selecting one magnetic memory cell group from the hierarchized magnetic memory cell groups according to an external temperature.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.

Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.

Abstract: A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.

Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.

Abstract: The present invention relates to a solid preparation including a Pelargonium sidoides extract and a silicic acid compound, which is allowed to be formulated in a solid form by direct adsorption of the Pelargonium sidoides extract onto a silicic acid compound, and a preparation method thereof. Since the solid preparation including the Pelargonium sidoides extract and the silicic acid compound of the present invention has higher stability than a liquid preparation such as syrup, and has no additives such as sugars, there is no concern about microbial contamination or spoilage of the preparation. In addition, it is possible to pack the solid preparation individually. Since the solid preparation is smaller in volume than the liquid preparation, it is highly portable, and there is also a convenience that no additional tools are needed to take the drug. Further, the active ingredient can be taken at the equal amount every time.

Abstract: A method of writing data using a coercivity distribution of a data storage medium, including mapping the coercivity distribution of the data storage medium including a plurality of write spots in which data can be written, measuring a current ambient temperature, and if the ambient temperature is higher than a room temperature, selecting a write spot having a relatively large coercivity to receive write data, and if the ambient temperature is lower than the room temperature, selecting a write spot having a relatively small coercivity to receive the write data.

Abstract: A method of writing data using a coercivity distribution of a data storage medium, including mapping the coercivity distribution of the data storage medium including a plurality of write spots in which data can be written, measuring a current ambient temperature, and if the ambient temperature is higher than a room temperature, selecting a write spot having a relatively large coercivity to receive write data, and if the ambient temperature is lower than the room temperature, selecting a write spot having a relatively small coercivity to receive the write data.

Abstract: A frequency tracking method and apparatus is provided. A receiver receives OFDM symbols and determines associated frequency offset. A frequency error estimator selects a cross correlation window for determining frequency offset based on timing offset. A symbol timing estimator is used to determine the timing offset.

Abstract: Methods and apparatus for frequency tracking of a received signal. In an aspect, a method is provided wherein the received signal comprises one or more symbols having a periodic structure. The method comprises receiving a plurality of samples of a selected symbol that comprises pilot signals scrambled with data and determining a window size and a periodicity factor. The method also comprises accumulating a correlation between samples in a first window and samples in a second window to produce an accumulated correlation value, wherein the first and second windows have a size and a separation based on the window size and the periodicity factor, respectively, and deriving a frequency error estimate based on the accumulated correlation value.

Abstract: Techniques for performing frequency control using dual-loop automatic frequency control (AFC) are described. The dual-loop AFC includes an inner loop that corrects short-term frequency variations (e.g., due to Doppler effect) and an outer loop that corrects long-term frequency variations (e.g., due to component tolerances and temperature variations). In one design, a first inner loop is implemented for frequency control of a first system (e.g., a broadcast system), a second inner loop is implemented for frequency control of a second system (e.g., a cellular system), and at least one outer loop is implemented for adjusting a reference frequency used to receive signals from the first and second systems. Each inner loop estimates and corrects the frequency error in an input signal for the associated system and may be enabled when receiving the input signal from the system. The reference frequency may be used for frequency downconversion, sampling and/or other purposes.

Abstract: Channel estimation in a spectrally shaped wireless communication system in which an initial frequency response estimate is obtained for a first set of P uniformly spaced subbands (1) based on pilot symbols received on a second set of subbands used for pilot transmission and (2) using extrapolation and/or interpolation. A channel impulse response estimate is obtained by performing an IFFT on a frequency response estimate. The number of taps in the channel impulse response can be truncated to a predetermined number of taps determined based on an operating mode of the second set of P uniformly spaced subbands. The energy of each tap value remaining after truncation can be compared to a predetermined threshold and modified based on the results of the comparison. The predetermined threshold can be determined based on an operating mode. A final frequency response estimate for each mode within each OFDM symbol is derived.

Abstract: Dynamic channel estimation thresholds allow for determining optimal threshold values for channel estimation in a layered-modulation wireless communication system. A channel estimation threshold can be used to remove or otherwise filter out channel estimate components that may be significantly influenced by noise. The channel estimation threshold value can be used to generate a refined channel estimate that is used in decoding multiple layers of a layered modulation signal. The channel estimation threshold value can be varied based on the performance of the various signal layer decoders. The adaptive channel estimation threshold provides for decoding a base layer based on an optimal threshold value for the base layer; determining an error rate associated with decoding the base layer; and using an optimal threshold value for an enhancement layer in a channel estimation algorithm if the error rate is lower than a predetermined level.