Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

Abstract: Provided is a method of producing a composite solid electrolyte. The method includes step S10 of producing an oxide-based solid electrolyte membrane by electrospinning a mixture including an oxide-based solid electrolyte precursor and a polymer, step S20 of producing an oxide-based solid electrolyte support by removing the polymer inside the oxide-based solid electrolyte membrane, and step S30 of causing the oxide-based solid electrolyte support to be impregnated with a sulfide-based solid electrolyte using a sulfide-based solid electrolyte precursor solution including a sulfide-based solid electrolyte precursor and a solvent.

Abstract: A flexible battery may include: an electrode assembly having one or more unit cells each of the unit cells including a pair of electrode plates having different polarities, a separator interposed between the respective electrode plates and electrode tabs that protrude from the respective electrode plates; a pair of electrode leads connected to electrode tabs; and a strengthening tab fixed on any one electrode lead connection tab among the electrode tabs.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: Provided is a method of operating a magnetic memory system. The method of operating the magnetic memory system includes: preparing a plurality of magnetic memory cells; classifying the magnetic memory cells into a plurality of magnetic memory cell groups by using program current values of the magnetic memory cells; constructing a magnetic memory system by hierarchizing the magnetic memory cell groups; and primarily performing programming by selecting one magnetic memory cell group from the hierarchized magnetic memory cell groups according to an external temperature.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.

Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.

Abstract: A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.

Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.

Abstract: The present invention relates to a solid preparation including a Pelargonium sidoides extract and a silicic acid compound, which is allowed to be formulated in a solid form by direct adsorption of the Pelargonium sidoides extract onto a silicic acid compound, and a preparation method thereof. Since the solid preparation including the Pelargonium sidoides extract and the silicic acid compound of the present invention has higher stability than a liquid preparation such as syrup, and has no additives such as sugars, there is no concern about microbial contamination or spoilage of the preparation. In addition, it is possible to pack the solid preparation individually. Since the solid preparation is smaller in volume than the liquid preparation, it is highly portable, and there is also a convenience that no additional tools are needed to take the drug. Further, the active ingredient can be taken at the equal amount every time.

Abstract: A method of writing data using a coercivity distribution of a data storage medium, including mapping the coercivity distribution of the data storage medium including a plurality of write spots in which data can be written, measuring a current ambient temperature, and if the ambient temperature is higher than a room temperature, selecting a write spot having a relatively large coercivity to receive write data, and if the ambient temperature is lower than the room temperature, selecting a write spot having a relatively small coercivity to receive the write data.

Abstract: A method of writing data using a coercivity distribution of a data storage medium, including mapping the coercivity distribution of the data storage medium including a plurality of write spots in which data can be written, measuring a current ambient temperature, and if the ambient temperature is higher than a room temperature, selecting a write spot having a relatively large coercivity to receive write data, and if the ambient temperature is lower than the room temperature, selecting a write spot having a relatively small coercivity to receive the write data.

Abstract: A frequency tracking method and apparatus is provided. A receiver receives OFDM symbols and determines associated frequency offset. A frequency error estimator selects a cross correlation window for determining frequency offset based on timing offset. A symbol timing estimator is used to determine the timing offset.