Patents by Inventor Seong-Do Kim

Seong-Do Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8013641
    Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: September 6, 2011
    Assignee: Electronics and Telecommunications Resarch Instittute
    Inventors: Ja Yol Lee, Seong Do Kim, Mun Yang Park, Cheon Soo Kim, Hyun Kyu Yu
  • Publication number: 20110204944
    Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ja Yol LEE, Seong Do KIM, Mun Yang PARK, Cheon Soo KIM, Hyun Kyu YU
  • Publication number: 20110202302
    Abstract: An apparatus and method for identifying a human being and an animal are disclosed to properly identifying whether or not a target is a human being or an animal. The apparatus for distinguishing between a human being and an animal includes: a target stimulation unit generating a stimulation signals for selectively stimulating the senses of a human being and an animal and providing the generated stimulation signal to a target; and a target identifying unit detecting the reaction of a target to the simulation signal to identify whether or not the target is a human being or an animal.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 18, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Pil Jae PARK, Hyun Kyu Yu, Seong Do Kim, Sung Chul Woo
  • Publication number: 20110150138
    Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 23, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jung Woo PARK, Young Jae Lee, Hyun Kyu Yu, Byung Hun Min, Seong Do Kim, Hoai Nam Nguyen, Sang Gug Lee
  • Publication number: 20110148490
    Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ja Yol Lee, Seon Ho Han, Mi Jeong Park, Jang Hong Choi, Seong Do Kim, Hyun Kyu Yu
  • Publication number: 20110150125
    Abstract: There are provided a digital RF converter capable of improving a dynamic range and a signal to noise ratio of a transmitter and a digital RF modulator and a transmitter including the same. The digital RF converter may include: a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed; a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed; and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyun Kyu YU, Jang Hong Choi, Hyun Ho Boo, Pil Jae Park, Mun Yang Park, Seong Do Kim, Sun Bo Shim, Song Cheol Hong
  • Patent number: 7956658
    Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 7, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Ja Yol Lee, Seong Do Kim, Mun Yang Park, Cheon Soo Kim, Hyun Kyu Yu
  • Patent number: 7933369
    Abstract: Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: April 26, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jang Hong Choi, Seong Do Kim, Hyun Kyu Yu
  • Publication number: 20100271072
    Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
    Type: Application
    Filed: October 28, 2009
    Publication date: October 28, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ja Yol LEE, Seong Do Kim, Mun Yang Park, Cheon Soo Kim, Hyun Kyu Yu
  • Publication number: 20100144281
    Abstract: An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 10, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Seong Do KIM, Ja Yol LEE, Jae Hoon SHIM, Hyun Kyu YU
  • Publication number: 20100134192
    Abstract: A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.
    Type: Application
    Filed: October 16, 2009
    Publication date: June 3, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Byung Hun MIN, Ja Yol Lee, Seong Do Kim, Cheon Soo Kim, Hyun Kyu Yu
  • Publication number: 20100134195
    Abstract: There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 3, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ja Yol LEE, Byung Hun Min, Seong Do Kim, Hyun Kyu Yu
  • Patent number: 7626476
    Abstract: A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: December 1, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Cheon Soo Kim, Myung Shin Kwak, Seong Do Kim, Mun Yang Park, Hyun Kyu Yu, Hee Bum Jung
  • Publication number: 20070241844
    Abstract: A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
    Type: Application
    Filed: March 23, 2007
    Publication date: October 18, 2007
    Inventors: Cheon Soo KIM, Myung Shin KWAK, Seong Do KIM, Mun Yang PARK, Hyun Kyu YU, Hee Bum JUNG
  • Patent number: 6615398
    Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: September 2, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Lee-Sup Kim, Ki-Hyuk Sung, Byung-Do Yang, Young-Jun Kim
  • Patent number: 6605996
    Abstract: An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity. The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: August 12, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Kyu Yu, Sang-Gug Lee, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Seon-Ho Han, Nam-Soo Kim
  • Publication number: 20030134611
    Abstract: The present invention relates to a local oscillator balun using an inverting circuit. The local oscillator balun using an inverting circuit comprises a complementary output converting circuit for amplifying a weak signal as a single signal from a local oscillator to produce two signals; a differential amplification circuit for producing two signals having a given amplitude from the two signals of said complementary output converting circuit; and an inverting circuit for inverting the two signals of the differential amplification circuit. Thus, a complementary signal having the maximum amplification and small phase difference can be produced. Therefore, the present invention can implement the maximum gain and small local oscillating leakage of the frequency mixer in a Gilbert type high frequency double balance frequency mixer.
    Type: Application
    Filed: June 24, 2002
    Publication date: July 17, 2003
    Inventors: Mun Yang Park, Seong Do Kim, Hyun Kyu Yu, Kyung Soo Kim
  • Publication number: 20030102916
    Abstract: An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
    Type: Application
    Filed: December 31, 2001
    Publication date: June 5, 2003
    Inventors: Hyun Kyu Yu, Sang-Gug Lee, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Seon-Ho Han, Nam-Soo Kim
  • Publication number: 20030090339
    Abstract: The present invention relates to an integrated filter circuit for digitally controlling characteristics of inductor and capacitor to thereby produce a controlled resonant frequency. The integrated circuit includes a number of inductors being connected in series between a high frequency input node and a high frequency output node, a plurality of capacitors each connected to a connection node of said each inductors, a plurality of switches, each connected between each capacitor and a ground and a feedback control unit for controlling the switches by sensing an output signal from the high frequency output node to thereby selectively couple each capacitor to the ground through a selected switches based on the sensed output signal.
    Type: Application
    Filed: December 28, 2001
    Publication date: May 15, 2003
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Piljae Park, Nam-Soo Kim, Cheon Soo Kim, Yong-Sik Youn
  • Publication number: 20030014721
    Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e.
    Type: Application
    Filed: December 18, 2001
    Publication date: January 16, 2003
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Lee-Sup Kim, Ki-Hyuk Sung, Byung-Do Yang, Young-Jun Kim