Patents by Inventor Seong Dong Kim
Seong Dong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170179259Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.Type: ApplicationFiled: July 28, 2016Publication date: June 22, 2017Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
-
Publication number: 20170179303Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.Type: ApplicationFiled: July 11, 2016Publication date: June 22, 2017Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
-
Patent number: 9431305Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.Type: GrantFiled: December 18, 2015Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
-
Publication number: 20160172361Abstract: Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventors: Hwa-Sung Rhee, Seung-Chul LEE, Chul-Wan AN, Henry K. UTOMO, Seong-Dong KIM
-
Patent number: 9171935Abstract: A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.Type: GrantFiled: March 7, 2014Date of Patent: October 27, 2015Assignee: GlobalFoundries Inc.Inventors: Seong-Dong Kim, Myung-Hee Na, Jin Z. Wallner, Thomas A. Wallner, Qintao Zhang
-
Publication number: 20150255569Abstract: A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Seong-Dong Kim, Myung-Hee Na, Jin Z. Wallner, Thomas A. Wallner, Qintao Zhang
-
Publication number: 20130149830Abstract: Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Inventors: Hwa-Sung RHEE, Seung-Chul Lee, Chul-Wan An, Henry K. Utomo, Seong-Dong Kim
-
Patent number: 8299509Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.Type: GrantFiled: April 1, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Seong-Dong Kim, Zhijong Luo, Huilong Zhu
-
Patent number: 8293556Abstract: There are provided a micro gas sensor and a method for fabricating the same that comprises a micro heater formed inside a polysilicon membrane by doping impurities into a specific region of the polysilicon membrane positioned under a gas sensing substance, thereby improving thermal structural stability and making it easy to form the gas sensing substance. The micro gas sensor comprises: a micro heater formed by doping impurities into polysilicon vapor-deposited on a substrate on which a first insulating layer is formed; a polysilicon membrane for decreasing a heat loss of the micro heater; a power electrode for supplying power and a temperature measurement electrode for measuring a temperature, positioned at both ends of the micro heater; a second insulating layer formed on the micro heater; a sensing substance formed on the second insulating layer, for sensing a gas; and a sensing electrode for measuring a change in properties of the sensing substance.Type: GrantFiled: December 26, 2008Date of Patent: October 23, 2012Assignee: Korea Electronics Technology InstituteInventors: Kwang Bum Park, Seong Dong Kim, Joon Shik Park, Min Ho Lee
-
Patent number: 8022496Abstract: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.Type: GrantFiled: October 17, 2007Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Alvin J. Joseph, Seong-dong Kim, Louis D. Lanzerotti, Xuefeng Liu, Robert M. Rassel
-
Publication number: 20110180852Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.Type: ApplicationFiled: April 1, 2011Publication date: July 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Seong-Dong Kim, Zhijiong Luo, Huilong Zhu
-
Patent number: 7977178Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.Type: GrantFiled: March 2, 2009Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Seong-Dong Kim, Zhijiong Lou, Huilong Zhu
-
Patent number: 7927968Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.Type: GrantFiled: May 22, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Deok-Kee Kim, Seong-Dong Kim, Oh-Jung Kwon
-
Patent number: 7885251Abstract: A network configuration method of a sensor network configured to collect sensed data from a plurality of sensor nodes comprising: arranging linearly a path of respective node so as to enable all sensor nodes except for a sink node and a terminal node to have respectively a predecessor and a successor; and setting the time synchronization of whole network by fixing the each node take its own time synchronization on the basis of an operation section of the predecessor.Type: GrantFiled: December 27, 2005Date of Patent: February 8, 2011Assignee: Korea Electronics Technology InstituteInventors: Jae-Ho Kim, Sang-Shin Lee, Il-Yeup Ahn, Kwang-Ho Won, Seong-Dong Kim
-
Patent number: 7863201Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.Type: GrantFiled: March 12, 2009Date of Patent: January 4, 2011Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Infineon Technologies North America Corp., Infineon Technologies AGInventors: Yong-Kuk Jeong, Bong-Seok Suh, Dong-Hee Yu, Oh-Jung Kwon, Seong-Dong Kim, O Sung Kwon
-
Publication number: 20100314700Abstract: There are provided a micro gas sensor and a method for fabricating the same that comprises a micro heater formed inside a polysilicon membrane by doping impurities into a specific region of the polysilicon membrane positioned under a gas sensing substance, thereby improving thermal structural stability and making it easy to form the gas sensing substance. The micro gas sensor comprises: a micro heater formed by doping impurities into polysilicon vapor-deposited on a substrate on which a first insulating layer is formed; a polysilicon membrane for decreasing a heat loss of the micro heater; a power electrode for supplying power and a temperature measurement electrode for measuring a temperature, positioned at both ends of the micro heater; a second insulating layer formed on the micro heater; a sensing substance formed on the second insulating layer, for sensing a gas; and a sensing electrode for measuring a change in properties of the sensing substance.Type: ApplicationFiled: December 26, 2008Publication date: December 16, 2010Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTEInventors: Kwang Bum Park, Seong Dong Kim, Joon Shik Park, Min Ho Lee
-
Patent number: 7796958Abstract: A transmitter and a transmitting method of a wireless communication system are provided. The transmitter transmits RF signals using an outphasing scheme of converting one analog IF NC-EMS into two analog C-EMSs. In the transmitter, a baseband processor generates a baseband digital modulated I-signal and a baseband digital modulated Q-signal. A signal converter converts the baseband digital modulated I-signal and the baseband digital modulated Q-signal into a baseband analog modulated I-signal and a baseband analog modulated Q-signal. An IF processor up-converts the baseband analog modulated I-signal and the baseband analog modulated Q-signal to generate one analog IF NC-EMS. A signal component separator separates the analog IF NC-EMS into a first analog IF C-EMS and a second analog IF C-EMS. An RF processor up-converts the first analog IF C-EMS and the second analog IF C-EMS to generate a first analog RF C-EMS and a second analog RF C-EMS.Type: GrantFiled: August 30, 2007Date of Patent: September 14, 2010Assignee: Korea Electronics Technology InstituteInventors: Hae-Moon Seo, Yeon-Kuk Moon, Young-Kuk Park, Kwang-Ho Won, Seong-Dong Kim
-
Publication number: 20100219450Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.Type: ApplicationFiled: March 2, 2009Publication date: September 2, 2010Applicant: International Business Machines CorporationInventors: Seong-Dong Kim, Zhijiong Luo, Huilong Zhu
-
Patent number: 7783268Abstract: A transmitter and a transmitting method of a wireless communication system are provided. The transmitter transmits RF signals using an outphasing scheme of converting one analog IF NC-EMS into two analog C-EMSs. In the transmitter, a baseband processor generates a baseband digital modulated I-signal and a baseband digital modulated Q-signal. An IF processor up-converts the baseband digital modulated I-signal and the baseband digital modulated Q-signal to generate one digital IF NC-EMS. A signal component separator separates the digital IF NC-EMS into a first digital IF C-EMS and a second digital IF C-EMS. An RF processor up-converts the first digital IF C-EMS and the second digital IF C-EMS to generate a first analog RF C-EMS and a second analog RF C-EMS. A power amplifier amplifies powers of the first and second analog RF C-EMSs. An RF combiner combines the first and second analog RF C-EMSs having the amplified powers to generate one combined analog RF C-EMS.Type: GrantFiled: August 30, 2007Date of Patent: August 24, 2010Assignee: Korea Electronics Technology InstituteInventors: Hae-Moon Seo, Yeon-Kuk Moon, Young-Kuk Park, Kwang-Ho Won, Seong-Dong Kim
-
Publication number: 20100197124Abstract: A semiconductor integrated circuit device with enhanced reliability is provided. The semiconductor integrated circuit device includes a semiconductor substrate; a gate insulation film that is provided on the semiconductor substrate; a gate electrode that is provided on the gate insulation film; and a sidewall spacer that is provided on side walls of the gate insulation film and the gate electrode and includes, wherein the sidewall spacer has a first sidewall spacer in contact with the gate electrode and a second sidewall spacer formed on the side walls of the first sidewall spacer, and a ratio of an Si—OH area to an Si—O area in at least one of the first and second sidewall spacers is 0.05 or less, as measured by Fourier Transform InfraRed (FTIR).Type: ApplicationFiled: February 2, 2009Publication date: August 5, 2010Inventors: Yong-kuk Jeong, Dong-hee Yu, Jong-ho Yang, Seong-dong Kim