Patents by Inventor Seong-Geon Park
Seong-Geon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11037988Abstract: A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.Type: GrantFiled: February 27, 2020Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Uk Kim, Jeong Hee Park, Seong Geon Park, Soon Oh Park, Jung Moo Lee
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Patent number: 10714685Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: GrantFiled: August 1, 2019Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kyu Yang, Seong Geon Park, Dong Jun Seong, Dong Ho Ahn, Jung Moo Lee, Seol Choi, Hideki Horii
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Publication number: 20200194500Abstract: A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.Type: ApplicationFiled: February 27, 2020Publication date: June 18, 2020Inventors: Jong Uk KIM, Jeong Hee PARK, Seong Geon PARK, Soon Oh PARK, Jung Moo LEE
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Patent number: 10636968Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.Type: GrantFiled: February 15, 2019Date of Patent: April 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hideki Horii, Seong-Geon Park, Dong-Ho Ahn, Jung-Moo Lee
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Publication number: 20190355905Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Min Kyu YANG, Seong Geon PARK, Dong Jun SEONG, Dong Ho AHN, Jung Moo LEE, Seol CHOI, Hideki HORN
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Patent number: 10403818Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: GrantFiled: January 9, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kyu Yang, Seong Geon Park, Dong Jun Seong, Dong Ho Ahn, Jung Moo Lee, Seol Choi, Hideki Horii
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Publication number: 20190189920Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.Type: ApplicationFiled: February 15, 2019Publication date: June 20, 2019Inventors: Hideki Horii, Seong-Geon Park, Dong-Ho Ahn, Jung-Moo Lee
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Patent number: 10236444Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.Type: GrantFiled: February 14, 2017Date of Patent: March 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hideki Horii, Seong-Geon Park, Dong-Ho Ahn, Jung-Moo Lee
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Patent number: 10186552Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.Type: GrantFiled: March 1, 2017Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seol Choi, Hideki Horii, Dong-ho Ahn, Seong-geon Park, Dong-jun Seong, Min-kyu Yang, Jung-moo Lee
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Publication number: 20190013357Abstract: A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.Type: ApplicationFiled: June 26, 2018Publication date: January 10, 2019Inventors: Jong Uk KIM, Jeong Hee PARK, Seong Geon PARK, Soon Oh PARK, Jung Moo LEE
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Publication number: 20180047899Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.Type: ApplicationFiled: February 14, 2017Publication date: February 15, 2018Inventors: HIDEKI HORII, SEONG-GEON PARK, DONG-HO AHN, JUNG-MOO LEE
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Publication number: 20180040818Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.Type: ApplicationFiled: January 9, 2017Publication date: February 8, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Min Kyu YANG, Seong Geon PARK, Dong Jun SEONG, Dong Ho AHN, Jung Moo LEE, Seol CHOI, Hideki HORII
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Publication number: 20180033826Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.Type: ApplicationFiled: March 1, 2017Publication date: February 1, 2018Inventors: Seol Choi, Hideki Horii, Dong-ho Ahn, Seong-geon Park, Dong-jun Seong, Min-kyu Yang, Jung-moo Lee
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Patent number: 9293700Abstract: According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.Type: GrantFiled: June 11, 2014Date of Patent: March 22, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Ju, Min-Kyu Yang, Eun-Mi Kim, Seong-Geon Park
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Publication number: 20140291605Abstract: According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventors: Hyun-Su JU, Min-Kyu YANG, Eun-Mi KIM, Seong-Geon PARK
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Patent number: 8785899Abstract: According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.Type: GrantFiled: August 16, 2012Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., LtdInventors: Hyun-Su Ju, Min-Kyu Yang, Eun-Mi Kim, Seong-Geon Park
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Publication number: 20130200326Abstract: According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.Type: ApplicationFiled: August 16, 2012Publication date: August 8, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Su JU, Min-Kyu YANG, Eun-Mi KIM, Seong-Geon PARK
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Patent number: 7892958Abstract: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.Type: GrantFiled: April 13, 2009Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Lan Lee, Yu-Gyun Shin, Sang-Bom Kang, Hag-Ju Cho, Seong-Geon Park, Taek-Soo Jeon
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Patent number: 7833855Abstract: In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electrode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR1)(NR2R3)3, in which R1, R2 and R3 represent H or a C1-C6 alkyl group, may be used to form the metal nitride layer. Nitrogen may then be implanted into the metal nitride layer to increase the nitrogen content of the layer.Type: GrantFiled: June 26, 2006Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Bom Kang, Kyung-In Choi, You-Kyoung Lee, Seong-Geon Park, Gil-Heyun Choi, Jong-Myeong Lee, Sang-Woo Lee
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Publication number: 20090253256Abstract: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.Type: ApplicationFiled: April 13, 2009Publication date: October 8, 2009Inventors: Hye-Lan Lee, Yu-Gyun Shin, Sang-Bom Kang, Hag-Ju Cho, Seong-Geon Park, Taek-Soo Jeon