Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

Abstract: A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.

Abstract: A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.

Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.