Patents by Inventor Seong-Gyun Kim

Seong-Gyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7037781
    Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: May 2, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim
  • Publication number: 20060044915
    Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 2, 2006
    Inventors: Ji-Hoon Park, Seung-Beom Yoon, Jeong-Uk Han, Seong-Gyun Kim, Sung-Taeg Kang, Bo-Young Seo, Sang-Woo Kang, Sung-Woo Park
  • Patent number: 6995742
    Abstract: A flat panel display device for a small module application is disclosed in the present invention.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: February 7, 2006
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Jae Deok Park, Seong-Gyun Kim
  • Publication number: 20060006452
    Abstract: Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.
    Type: Application
    Filed: March 23, 2005
    Publication date: January 12, 2006
    Inventors: Ji-Hoon Park, Sung-Taeg Kang, Seong-Gyun Kim, Bo-Young Seo, Sung-Woo Park
  • Publication number: 20050258472
    Abstract: A nonvolatile semiconductor memory device includes: a gate stack which has a tunnel oxide film, a floating gate, an interlayer insulating film and a control gate sequentially formed on a semiconductor substrate; a first diffusion region which is formed in the semiconductor substrate on one side surface of the gate stack; a second diffusion region which is formed in the semiconductor substrate on the other side surface of the gate stack; and a channel region which is formed in the semiconductor substrate between the first and second diffusion regions, wherein the floating gate has both side surfaces wave-shaped in the direction of a channel length.
    Type: Application
    Filed: April 18, 2005
    Publication date: November 24, 2005
    Inventors: Sung-Taeg Kang, Seong-Gyun Kim, Ji-Hoon Park
  • Publication number: 20050255657
    Abstract: A nonvolatile memory device is formed by forming a first oxide layer on a substrate. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. The second oxide layer is patterned so as to expose the nitride layer. A first polysilicon layer is formed on the second oxide layer and the exposed portion of the nitride layer. The first polysilicon layer and the nitride layer are etched so as to expose the second oxide layer and the first oxide layer and to form polysilicon spacers on the nitride layer. The polysilicon spacers are etched so as to expose portions of the nitride layer. The exposed portions of the nitride layer may function as charge trapping layers. The exposed portion of the first oxide layer is etched to expose a portion of the substrate. A third oxide layer is formed on the exposed portion of the substrate, the exposed portions of the nitride layer, and the second oxide layer. A second polysilicon layer is formed on the third oxide layer.
    Type: Application
    Filed: June 28, 2005
    Publication date: November 17, 2005
    Inventor: Seong-gyun Kim
  • Publication number: 20050243033
    Abstract: An organic electro luminescence device includes first, second, and third switching elements connected in series with each other, the first switching element controlled by a first signal, and the second and third switching elements controlled by a second signal, the second signal being different from the first signal, a first driving element connected to a power source, a storage capacitor, and the first, second and third switching elements, and a second driving element connected to the power source, the storage capacitor, an organic light emitting diode, and the third switching element.
    Type: Application
    Filed: October 14, 2004
    Publication date: November 3, 2005
    Inventors: Seong-Gyun Kim, Du-Hwan Oh
  • Publication number: 20050218444
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Application
    Filed: May 20, 2005
    Publication date: October 6, 2005
    Inventor: Seong-Gyun Kim
  • Patent number: 6927131
    Abstract: A nonvolatile memory device is formed by forming a first oxide layer on a substrate. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. The second oxide layer is patterned so as to expose the nitride layer. A first polysilicon layer is formed on the second oxide layer and the exposed portion of the nitride layer. The first polysilicon layer and the nitride layer are etched so as to expose the second oxide layer and the first oxide layer and to form polysilicon spacers on the nitride layer. The polysilicon spacers are etched so as to expose portions of the nitride layer. The exposed portions of the nitride layer may function as charge trapping layers. The exposed portion of the first oxide layer is etched to expose a portion of the substrate. A third oxide layer is formed on the exposed portion of the substrate, the exposed portions of the nitride layer, and the second oxide layer. A second polysilicon layer is formed on the third oxide layer.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: August 9, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-gyun Kim
  • Patent number: 6922361
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: July 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-Gyun Kim
  • Patent number: 6912162
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 28, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-Gyun Kim
  • Patent number: 6900089
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: May 31, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-Gyun Kim
  • Publication number: 20050106816
    Abstract: A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 19, 2005
    Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim, Jae-Hwang Kim
  • Publication number: 20050054167
    Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.
    Type: Application
    Filed: July 9, 2004
    Publication date: March 10, 2005
    Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim
  • Publication number: 20050051835
    Abstract: An electrically erasable and programmable read only memory (EEPROM) device may include: a gate oxide layer on a semiconductor substrate, the gate oxide layer including a first segment of a first thickness, a second segment of a second thickness, and a tunneling third segment of a third thickness, the second thickness being thicker than the first thickness and the third thickness being thinner than the first thickness; a floating junction region formed under a portion of the gate oxide layer in the semiconductor substrate; and a floating gate, an insulating layer pattern, and a control gate which are sequentially formed, respectively, on the gate oxide layer.
    Type: Application
    Filed: May 20, 2004
    Publication date: March 10, 2005
    Inventors: Sung-Taeg Kang, Seong-Gyun Kim
  • Patent number: 6861699
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device according to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: March 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-Gyun Kim
  • Patent number: 6844589
    Abstract: A non-volatile SONOS memory device includes a semiconductor substrate having a source region and a drain region. A channel is formed between the source region and the drain region. A gate insulation layer including a nitride layer is formed over the channel, and a gate is formed over the gate insulation layer. The channel is a stepped channel including a top part, an inclined part and a bottom part. The nitride layer is formed over the inclined part and the bottom part, and the top part of the channel is adjacent to the source region and the bottom part of the channel is adjacent to the drain region.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: January 18, 2005
    Assignee: Samsung Electronics, Co., LTD
    Inventor: Seong-Gyun Kim
  • Publication number: 20050002226
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Application
    Filed: June 8, 2004
    Publication date: January 6, 2005
    Inventor: Seong-Gyun Kim
  • Publication number: 20040223356
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Seong-Gyun Kim
  • Publication number: 20040219734
    Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device according to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 4, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Seong-Gyun Kim