Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode.

Abstract: A memory device includes a memory cell array including a plurality of memory cells and cell select circuitry configured to selectively connect the plurality of memory cells to a data line, e.g., a common output node of a column selecting gate circuit. The device further includes a bias circuit operative to charge the data line to a bias voltage responsive to a bias enable signal, and a sense amplifier circuit having an input coupled to the data line and including an output buffer. The sense amplifier circuit is operative to drive the output buffer according to a voltage on the data line responsive to a sense enable signal to thereby generate a sense amplifier output signal indicative of a state of a memory cell connected to the data line.

Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A semiconductor memory device and method of reading data from the semiconductor memory device is described. The semiconductor memory device may generate a data read clock signal that changes from a first logic state to a second logic state, and may read out bit cell data from a plurality of bit lines based on the generated data read clock signal. A word line signal and a dummy word line signal may be activated from the first logic state to the second logic state based on incoming X-address signals and Y-address signals. An enable signal may be output based on the activated dummy word signal, and a sense amplifier may sense the read-out bit cell data and a reference signal based on the activated enable signal, and output a corresponding to the sensed read-out bit cell data.

Abstract: A semiconductor memory device and method of reading data from the semiconductor memory device is described. The semiconductor memory device may generate a data read clock signal that changes from a first logic state to a second logic state, and may read out bit cell data from a plurality of bit lines based on the generated data read clock signal. A word line signal and a dummy word line signal may be activated from the first logic state to the second logic state based on incoming X-address signals and Y-address signals. An enable signal may be output based on the activated dummy word signal, and a sense amplifier may sense the read-out bit cell data and a reference signal based on the activated enable signal, and output a corresponding to the sensed read-out bit cell data.

Abstract: A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode.

Abstract: Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A ternary CAM cell includes a main memory cell, a mask memory cell, a match line, a mask circuit, and a comparison circuit, where the main memory cell is enabled to a wordline to store data, and the mask memory cell enabled to a wordline to store mask data, data transferred to/from the main memory cell is loaded on a bitline pair, and mask data transferred to a mask memory cell is loaded on a mask bitline pair, comparison data is loaded on a comparison signal line pair, while the mask circuit is coupled between the match line and the mask memory cell to receive the comparison data, and the comparison circuit is coupled between the mask circuit and a ground voltage and includes a pair of transistors coupled to a comparison signal line pair and a pair of match transistors coupled to the data of the main memory cell such that, although the voltage level of the comparison data is lowered, a low voltage operation characteristic is excellent, the capacitive loadings of comparison signal lines are constantly maintai

Abstract: Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated.

Abstract: A memory device includes a memory cell array including a plurality of memory cells and cell select circuitry configured to selectively connect the plurality of memory cells to a data line, e.g., a common output node of a column selecting gate circuit. The device further includes a bias circuit operative to charge the data line to a bias voltage responsive to a bias enable signal, and a sense amplifier circuit having an input coupled to the data line and including an output buffer. The sense amplifier circuit is operative to drive the output buffer according to a voltage on the data line responsive to a sense enable signal to thereby generate a sense amplifier output signal indicative of a state of a memory cell connected to the data line.

Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.

Abstract: Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated.