Abstract: A method of manufacturing a MIM capacitor and a interconnecting structure using a damascene process. The MIM capacitor and the first interconnecting structure can be formed at equal depths.

Abstract: A bonding pad in a semiconductor device can include a conductive plug pattern on a conductive layer, where the conductive layer includes a conductive material and a dummy pattern surrounded by the conductive material. Related methods are also disclosed.

Abstract: A method of manufacturing a MIM capacitor and a interconnecting structure using a damascene process. The MIM capacitor and the first interconnecting structure can be formed at equal depths.

Abstract: A bond pad of a semiconductor device capable of restraining dishing and having improved conductivity by a damascene technique using a copper pattern, includes first and second copper patterns of irregular lattice models, first and second dielectric layer patterns to connect the first and second copper patterns in the vertical direction, a line connection structure horizontally connecting the first and second copper patterns, and a conductivity improving layer formed on the first and second copper patterns. Dishing generated in planarizing the first and second copper patterns by a damascene technique can be restrained due to the first and second copper patterns of the lattice models. Also, the conductivity property of the bond pad can be improved by connecting the first and second copper patterns horizontally and in the vertical direction and further forming the conductivity improving layer on the first and second copper patterns.

Abstract: A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.

Abstract: A bond pad of a semiconductor device capable of restraining dishing and having improved conductivity by a damascene technique using a copper pattern, includes first and second copper patterns of irregular lattice models, first and second dielectric layer patterns to connect the first and second copper patterns in the vertical direction, a line connection structure horizontally connecting the first and second copper patterns, and a conductivity improving layer formed on the first and second copper patterns. Dishing generated in planarizing the first and second copper patterns by a damascene technique can be restrained due to the first and second copper patterns of the lattice models. Also, the conductivity property of the bond pad can be improved by connecting the first and second copper patterns horizontally and in the vertical direction and further forming the conductivity improving layer on the first and second copper patterns.

Abstract: A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.