Patents by Inventor Seong Hwan Myung
Seong Hwan Myung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7960231Abstract: A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved.Type: GrantFiled: June 27, 2008Date of Patent: June 14, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jung Geun Kim, Seong Hwan Myung, Eun Soo Kim
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Patent number: 7897504Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.Type: GrantFiled: May 11, 2007Date of Patent: March 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jung Geun Kim, Cheol Mo Jeong, Whee Won Cho, Seong Hwan Myung
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Patent number: 7652352Abstract: An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.Type: GrantFiled: June 29, 2007Date of Patent: January 26, 2010Assignee: Hynix Semiconductor Inc.Inventors: Whee Won Cho, Seong Hwan Myung, Eun Jung Ko
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Patent number: 7629213Abstract: A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.Type: GrantFiled: December 29, 2006Date of Patent: December 8, 2009Assignee: Hynix Semiconductor Inc.Inventors: Whee Won Cho, Jung Geun Kim, Seong Hwan Myung, Cheol Mo Jeong
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Patent number: 7560340Abstract: A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.Type: GrantFiled: December 6, 2006Date of Patent: July 14, 2009Assignee: Hynix Semiconductor Inc.Inventors: Whee Won Cho, Seung Hee Hong, Seong Hwan Myung, Eun Soo Kim
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Patent number: 7521319Abstract: A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.Type: GrantFiled: December 28, 2006Date of Patent: April 21, 2009Assignee: Hynix Semiconductor Inc.Inventors: Cheol Mo Jeong, Whee Won Cho, Jung Geun Kim, Seong Hwan Myung
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Publication number: 20090098722Abstract: A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved.Type: ApplicationFiled: June 27, 2008Publication date: April 16, 2009Applicant: Hynix Semiconductor Inc.Inventors: Jung Geun KIM, Seong Hwan Myung, Eun Soo Kim
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Patent number: 7482264Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.Type: GrantFiled: November 27, 2006Date of Patent: January 27, 2009Assignee: Hynix Semiconductor Inc.Inventors: Cheol Mo Jeong, Seong Hwan Myung, Eun Soo Kim, Suk Joong Kim
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Publication number: 20080268608Abstract: In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.Type: ApplicationFiled: December 6, 2007Publication date: October 30, 2008Applicant: Hynix Semiconductor Inc.Inventors: Suk Joong Kim, Whee Won Cho, Jung Geun Kim, Seong Hwan Myung
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Publication number: 20080224272Abstract: An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.Type: ApplicationFiled: June 29, 2007Publication date: September 18, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Whee Won Cho, Seong Hwan Myung, Eun Jung Ko
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Publication number: 20080220605Abstract: The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation layer on a region on which the trench is formed; forming a second conductive layer to make the second conductive layer contact with the first conductive layer; and removing the second conductive layer formed on the isolation layer.Type: ApplicationFiled: December 13, 2007Publication date: September 11, 2008Inventors: Jung Gu Lee, Whee Won Cho, Seong Hwan Myung, Suk Joong Kim
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Publication number: 20080105983Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.Type: ApplicationFiled: November 27, 2006Publication date: May 8, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Cheol Mo Jeong, Seong Hwan Myung, Eun Soo Kim, Suk Joong Kim
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Publication number: 20080102622Abstract: A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.Type: ApplicationFiled: December 27, 2006Publication date: May 1, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jung Geun Kim, Cheol Mo Jeong, Whee Won Cho, Seong Hwan Myung
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Publication number: 20080081465Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.Type: ApplicationFiled: May 11, 2007Publication date: April 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jung Geun Kim, Cheol-Mo Jeong, Whee-Won Cho, Seong-Hwan Myung
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Publication number: 20080003754Abstract: A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.Type: ApplicationFiled: December 28, 2006Publication date: January 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Cheol Mo Jeong, Whee Won Cho, Jung Geun Kim, Seong Hwan Myung
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Publication number: 20080003742Abstract: A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.Type: ApplicationFiled: December 6, 2006Publication date: January 3, 2008Applicant: Hynix Semiconductor Inc.Inventors: Whee Won Cho, Seung Hee Hong, Seong Hwan Myung, Eun Soo Kim
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Publication number: 20080003745Abstract: The present invention relates to a method of manufacturing a flash memory device. The method includes the steps of forming cell gate patterns and select transistor gate patterns on a semiconductor substrate; forming a low dielectric layer on the resultant structure; etching the low dielectric layer, leavinin gaps adjacent the cell gate patterns; and, forming a nitride layer spacer on one side wall of each of the select transistor gate patterns. The resulting flash memory device has an improved rate of change in the threshold voltage and reduces the contact resistance when a self-aligned contact method is subsequently performed.Type: ApplicationFiled: December 28, 2006Publication date: January 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Seong Hwan Myung, Jung Geun Kim, Whee Won Cho, Cheol Mo Jeong
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Publication number: 20080003724Abstract: A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.Type: ApplicationFiled: December 29, 2006Publication date: January 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Whee Won Cho, Jung Geun Kim, Seong Hwan Myung, Cheol Mo Jeong