Patents by Inventor Seong-hwee Cheong
Seong-hwee Cheong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8466052Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.Type: GrantFiled: February 11, 2010Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
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Patent number: 8404576Abstract: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.Type: GrantFiled: March 22, 2011Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park, Jong-Min Baek
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Publication number: 20120216954Abstract: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.Type: ApplicationFiled: April 30, 2012Publication date: August 30, 2012Inventors: Jin-ho PARK, Seong-hwee Cheong, Gil-heyun Choi, Sang-woo Lee, Ho-ki Lee
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Patent number: 8043922Abstract: A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.Type: GrantFiled: January 29, 2010Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-bum Lee, Tae-hong Ha, Seong-hwee Cheong
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Patent number: 7989892Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.Type: GrantFiled: June 12, 2009Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Jong-Min Baek, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20110171818Abstract: A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park, Jong-Min Baek
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Patent number: 7928498Abstract: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.Type: GrantFiled: April 22, 2009Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park, Jong-Min Baek
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Patent number: 7816257Abstract: In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.Type: GrantFiled: April 24, 2006Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hwee Cheong, Gil-Heyun Choi, Sang-Woo Lee, Jin-Ho Park
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Patent number: 7781849Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.Type: GrantFiled: December 3, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Seong-hwee Cheong, Gil-heyun Choi, Tae-ho Cha, Hee-sook Park, Byung-hak Lee, Jae-hwa Park
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Publication number: 20100210105Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.Type: ApplicationFiled: February 11, 2010Publication date: August 19, 2010Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
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Publication number: 20100197103Abstract: A method of fabricating a semiconductor device can include forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region, forming an offset spacer of a first material on the gate structure, performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, forming a material layer of a second material on the semiconductor substrate and the gate structures, forming a material layer of a third material, which has an etch selectivity with respect to the second material, on the material layer made of the second material, etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantatiType: ApplicationFiled: January 29, 2010Publication date: August 5, 2010Inventors: Jun-bum Lee, Tae-hong Ha, Seong-hwee Cheong
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Patent number: 7759248Abstract: A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.Type: GrantFiled: October 24, 2006Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hwee Cheong, Sang-Woo Lee, Jong-Won Hong, Seung-Gil Yang, Kyung-In Choi, Hyun-Bae Lee
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Patent number: 7666786Abstract: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD, depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD, annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure, stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted, and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.Type: GrantFiled: June 1, 2007Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-ho Yun, Gil-heyun Choi, Seong-hwee Cheong, Sug-woo Jung, Hyun-su Kim, Woong-hee Sohn
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Publication number: 20090315091Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layerType: ApplicationFiled: June 12, 2009Publication date: December 24, 2009Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Jong-Min Baek, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Hee-Sook Park
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Publication number: 20090267132Abstract: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.Type: ApplicationFiled: April 22, 2009Publication date: October 29, 2009Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park, Jong-Min Baek
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Publication number: 20090189229Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.Type: ApplicationFiled: December 3, 2008Publication date: July 30, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Seong-hwee Cheong, Gil-heyun Choi, Tae-ho Cha, Hee-sook Park, Byung-hak Lee, Jae-hwa Park
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Patent number: 7507627Abstract: In one embodiment, a nonvolatile memory device can be fabricated by forming first metallic dots on a charge storage film using first source gas, forming substitution dots on the charge storage film on which the first metallic dots are formed and forming second metallic dots using a second source gas.Type: GrantFiled: March 14, 2007Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hwee Cheong, Sang-Woo Lee, Jin-Ho Park, Seung-Gil Yang, Brad H. Lee
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Publication number: 20080214012Abstract: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.Type: ApplicationFiled: January 11, 2008Publication date: September 4, 2008Inventors: Jin-ho Park, Seong-hwee Cheong, Gil-heyun Choi, Sang-woo Lee, Ho-ki Lee
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Publication number: 20080136040Abstract: Methods of forming electrical interconnects include forming a first electrically insulating layer on a semiconductor substrate and then forming an opening in the first electrically insulating layer. A step is performed to line a sidewall of the opening with a nitrified first metal layer having a non-uniform nitrogen concentration therein. An electrically conductive pattern is formed in the opening. A second metal nitride layer is provided between the electrically conductive pattern and the nitrified first metal layer.Type: ApplicationFiled: July 16, 2007Publication date: June 12, 2008Inventors: Jin-Ho Park, Seong-Hwee Cheong, Gil-Heyun Choi, Sang-Woo Lee, Ho-Ki Lee
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Publication number: 20080003711Abstract: In one embodiment, a nonvolatile memory device can be fabricated by forming first metallic dots on a charge storage film using first source gas, forming substitution dots on the charge storage film on which the first metallic dots are formed and forming second metallic dots using a second source gas.Type: ApplicationFiled: March 14, 2007Publication date: January 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-Hwee CHEONG, Sang-Woo LEE, Jin-Ho PARK, Seung-Gil YANG, Brad H. LEE