Patents by Inventor Seong Hyoung Park

Seong Hyoung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Panel bottom sheet and display including the same
    Patent number: 11953958
    Abstract: A display includes: a display panel; and a panel bottom sheet disposed below the display panel, the panel bottom sheet including: a first heat dissipation layer; a second heat dissipation layer over the first heat dissipation layer, including a first opening formed completely through the second heat dissipation layer in a thickness direction; a heat dissipation coupling interlayer between the first heat dissipation layer and the second heat dissipation layer, and a heat dissipation substrate on the second heat dissipation layer.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: April 9, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kang Woo Lee, Boo Kan Ki, June Hyoung Park, Sun Hee Oh, Dong Hyeon Lee, Jeong In Lee, Hyuk Hwan Kim, Seong Sik Choi
  • Plural wells structure in a semiconductor device
    Patent number: 6114729
    Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: September 5, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventors: Seong Hyoung Park, Jong Kwan Kim
  • Plural wells structure in a semiconductor device and method for forming the same
    Patent number: 5880014
    Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: March 9, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventors: Seong Hyoung Park, Jong Kwan Kim