Abstract: A display device includes: a first substrate including a planar display area and a planar non-display area; a pad disposed beneath the first substrate in the non-display area; a target checking portion disposed beneath the first substrate in the non-display area and including at least a part of an area provided with the pad; and a light-blocking pattern disposed in the non-display area on the first substrate to cover the target checking portion and containing a discoloring material.

Abstract: A display device includes a timing controller configured to receive an image data signal and a plurality of clock signals and to generate a scan clock signal and a plurality of data clock signals, a scan driver configured to receive the scan clock signal, and a data driver configured to receive the data clock signals. The clock signals include first to nth clock signals, and the data clock signals include first to nth data clock signals generated from the first to nth clock signals (n?2), the first to nth clock signals having differing frequencies and the first to nth data clock signals having differing frequencies. Whenever a predetermined number of frame periods has elapsed, the timing controller halts transmission of one of the first to nth data clock signals to the data driver, and begins transmission of another one of the first to nth data clock signals thereto.

Abstract: A display device includes: a first substrate including a planar display area and a planar non-display area; a pad disposed beneath the first substrate in the non-display area; a target checking portion disposed beneath the first substrate in the non-display area and including at least a part of an area provided with the pad; and a light-blocking pattern disposed in the non-display area on the first substrate to cover the target checking portion and containing a discoloring material.

Abstract: A display device includes a timing controller configured to receive an image data signal and a plurality of clock signals and to generate a scan clock signal and a plurality of data clock signals, a scan driver configured to receive the scan clock signal, and a data driver configured to receive the data clock signals. The clock signals include first to nth clock signals, and the data clock signals include first to nth data clock signals generated from the first to nth clock signals (n?2), the first to nth clock signals having differing frequencies and the first to nth data clock signals having differing frequencies. Whenever a predetermined number of frame periods has elapsed, the timing controller halts transmission of one of the first to nth data clock signals to the data driver, and begins transmission of another one of the first to nth data clock signals thereto.

Abstract: A method of driving a display panel includes sequentially driving a first gate line and a second gate line of a display panel during an N-th frame to charge data signals to first row pixels electrically connected to the first gate line and the second gate line, sequentially driving a third gate line and a fourth gate line of the display panel during the N-th frame to charge the data signals to second row pixels electrically connected to the third gate line and the fourth gate line, sequentially driving the second gate line and the first gate line during an (N+1)-th frame to charge the data signals to the first row pixels, and sequentially driving the fourth gate line and the third gate line during the (N+1)-th frame to charge the data signals to the second row pixels. Thus, display quality of a display apparatus may be improved.

Abstract: A gate driver includes a shift register part and an output control part. The shift register part sequentially shifts a first pulse signal in response to a clock to output a second pulse signal. The output control part converts the second pulse signal based on a first control signal to output a main pulse signal to a main gate line, and converts the second pulse signal in response to the first control signal and a second control signal to output a sub pulse signal having an adjusted output timing and an adjusted pulse width to a sub gate line. Thus, a liquid crystal display device having the gate driver may improve display quality thereof and reduce a size thereof.

Abstract: A liquid crystal display device, comprises a liquid crystal display panel; a light source part disposed along at least one side of the liquid crystal display panel; a light source cover, the light source cover reflecting light emitted from the light source part to the liquid crystal display panel; a panel supporting part disposed under an edge part of the liquid crystal display panel to support the liquid crystal display panel; and an optical film disposed under the liquid crystal display panel, and comprising a first area facing the liquid crystal display panel, and a second area extending below the panel supporting part, the second area comprising a plurality of protrusion parts and a plurality of cut parts alternately formed at an end of the second area, and at least part of the protrusion parts are provided on the light source cover.

Abstract: A gate driver includes a shift register part and an output control part. The shift register part sequentially shifts a first pulse signal in response to a clock to output a second pulse signal. The output control part converts the second pulse signal based on a first control signal to output a main pulse signal to a main gate line, and converts the second pulse signal in response to the first control signal and a second control signal to output a sub pulse signal having an adjusted output timing and an adjusted pulse width to a sub gate line. Thus, a liquid crystal display device having the gate driver may improve display quality thereof and reduce a size thereof.