Abstract: A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction.

Abstract: The electronic ballast includes a power source circuit for transforming a conventional AC power source into a stepped-up DC voltage and a half-bridge type inverted, in response to a pair of switching driving signals, for switching the stepped-up DC voltage to make a high-intensity discharge lamp operate. The ballast also includes a digital controller for generating the pair of the switching driving signals, which have a predetermined dead time respectively between a switching-ON time interval of the switching driving signals and a phase difference of 180 degrees therebetween, in a way that frequencies of the pair of the switching driving signals are gradually shifted into some other stepped levels in turn within a predetermined bandwidth by a predetermined time interval and such a frequency shifting operation is cyclically repeated, to be supplied to the half-bridge type inverter.

Abstract: A method for forming trench isolation in the silicon substrate is disclosed. This method allows for an improved bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After a trench is formed, sidewall silicon dioxide is grown on the sidewall of the trench by a first oxidation process. Then, PE-TEOS is deposited on the silicon substrate and the sidewall of the trench. The PE-TEOS layer around the entrance of the trench is then etched back using argon gas. The second oxidation process or the first annealing proceeds to enhance the bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After the second oxidation process or the annealing, the trench is filled with O.sub.3 -TEOS, and then PE-TEOS is deposited over the O.sub.3 -TEOS layer. Finally, the second annealing process follows.

Abstract: The present invention relates to a thermal transfer ink layer composition, wherein polyvinylacetal resin and cellulose derivatives are used in a mixture for the binder in the thermal transfer ink layer composition of the sublimation thermal transfer ink ribbon, or the another type of a binder is mixed into the mixture of polyvinylacetal resin and cellulose derivatives and so used therein. As a result, the adhesion between the thermal transfer ink layer and substrate film, and the gradation property of printed images are improved as compared to the case in which the respective binders are used individually. More particularly, the present invention relates to the thermal transfer ink layer composition of the sublimation thermal transfer ink ribbon, which can yield high quality images by means of the aforementioned improvements.

Abstract: A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a plurality of insulating layers, interposed vertically between the plurality of metal layers. A metal wiring pattern is formed on each of the plurality of metal layers. The wiring patterns are separated by insulating spaces, and the insulating spaces in each of the plurality of metal layers are vertically shifted with regard to the neighboring one of the plurality of metal layers.

Abstract: A technique for setting a power saving access time of an image forming apparatus includes: checking the time that no image is formed, and producing a value corresponding to the checked time; calculating a power saving mode access time according to data corresponding to the checked time; and resetting a power saving mode access time to the calculated power saving mode access time.

Abstract: An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased.

Abstract: A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction.

Abstract: An electro-static discharge (ESD) protection circuit for a semiconductor device includes a primary ESD protection circuit including at least two diodes, the primary ESD protection circuit being located between a positive voltage and a negative voltage, and connected to input/output terminals of the semiconductor device, the primary ESD protection circuit bypassing any static electricity applied from the input/output terminals; and a secondary ESD protection circuit connected to the primary ESD protection circuit in parallel, the secondary ESD protection circuit including at least two diodes.

Abstract: A sync signal separating circuit of an image output apparatus includes an inversion amplifying section for providing a green video signal supplied from a video signal generator to be output as an output signal that is inverted and amplified, and a clipper receiving the output signal of the inversion amplifying section as an input signal to output a clipped output signal obtained by cutting over or below a prescribed amplitude. Here, the inversion amplifying section has an amplifying device, an input resistor and a feedback resistor, and the clipper has a diode having an anode connected to the output side of the inversion amplifying section and a load resistor having one side connected to a cathode of the diode and the other side grounded. Thus, the sync signal is accurately produced from the cathode of the diode without requiring a conventional horizontal sync signal detecting section.

Abstract: An improved electro-static discharge and latch-up prevention circuit capable of preventing circuit malfunctions caused by an electro-static discharge and permitting an integrated circuit, in which a bias condition is stable, to perform a signal input/output operation by applying an electro-static having a certain level having a limited range to the integrated circuit, which includes an electro-static discharge prevention unit provided in the interior of or at the outside of an integrated circuit and connected between a positive voltage and a negative voltage in series for preventing positive and negative electro-static discharges; a switching unit connected between the electro-static discharge prevention unit and the interior circuit of the integrated circuit chip for switching; and a control unit for outputting a control signal so as to control a switching operation of the switching unit.

Abstract: The present invention relates to a passively Q-switched laser with a dual-cavity configuration to obtain a symmetrical laser pulse with a short and variable pulse width. The passively Q-switched laser comprises: a laser medium and a passively Q-switching medium; a cavity mirror capable of fully reflecting the respective wavelengths emitted from the laser medium and the passively Q-switching medium; a main cavity mirror composed of a dichroic mirror having non-reflective characteristics for the light emitted from the passively Q-switching medium and reflective characteristics for the light emitted from the laser medium with a reflectivity of 10% or more; and, an auxiliary cavity mirror composed of a dichroic mirror having non-reflective characteristics for the light emitted from the laser medium and reflective characteristics for the light emitted from the passively Q-switching medium with a reflectivity of 10% or more and capable of moving transversely against the laser beam.

Abstract: A differentially encoded quadrature modulation method comprises the steps of setting an index corresponding to a phase variation value constituted of input data, forming a phase value to obtain a phase-modulated output phase value from a given table and forming a channel signal to obtain in-phase (I) and quadrature (Q) channel signals from a given table using the phase value. The apparatus for performing the above comprises a signal converter for converting serially input data into two binary signal trains, a signal forming portion for obtaining channel signals, a digital-to-analog converter for converting the respective signals into two analog signals, a baseband filter for baseband-pass-filtering the signals, a phase shifter for shifting a carrier by 90.degree., first and second multipliers for multiplying the filtered signals with the carrier and phase-shifted carrier, respectively, and a mixer for mixing the respectively obtained signals and outputting a combined signal.

Abstract: A bus interface circuit is for coupling between a microprocessor having an architecture in which address and data buses are separated and peripheral equipment having a multiplexing bus architecture. The bus interface circuit includes a first delay circuit for delaying a first address strobe signal of a microprocessor to obtain a first data strobe signal, a second delay circuit for delaying the first data strobe signal to obtain a second data strobe signal for the peripheral equipment, a logic circuit for multiplying an inverted first data strobe signal and the first address strobe signal to obtain a second address strobe signal for the peripheral equipment, a first buffer enabled by the first data strobe signal for transmitting address data of the microprocessor, and second buffer means enabled by the second address strobe signal for transmitting and receiving data information between the microprocessor and the peripheral equipment.

Abstract: A circuit for detecting odd and even numbered fields of a video signal includes a first counter circuit for counting a clock pulse input to detect a vertical synchronous pulse interval of the video signal, a second counter circuit for counting the clock pulse upon detection of the vertical synchronous pulse interval to generate a window signal and a counting signal having a predetermined pulse width, and an output circuit responsive to horizontal synchronous pulses and the window signal to generate a first logic state remaining for a next vertical synchronous pulse interval or generate a second logic state remaining for the next vertical synchronous pulse interval, whereby the output circuit maintains the first logic state for the odd field and the second logic state for the even field.

Abstract: The present invention relates to a frame buffer used by a laser printer controller to send video signals to a laser printer engine. The frame buffer allows software to have sufficient control over the dimension of the buffer and to have sufficient time to process data by allowing hardware assisted memory erase.

Abstract: The present invention relates to a frame buffer used by a laser printer controller to send video signals to a laser printer engine. The frame buffer allows software to have sufficient control of the dimension of the buffer and to have sufficient time to process data by allowing software to change X and Y dimensions of the buffer. In addition, software controls the loading of the frame buffer start address.

Abstract: The present invention relates to a frame buffer used by a laser printer controller to send video signals to a laser printer engine. The frame buffer allows software to have sufficient control of the dimension of the buffer and to have sufficient time to process data by allowing software to change X and Y dimensions of the buffer. In addition, software controls the loading of the frame buffer start address.

Abstract: The present invention relates to a frame buffer used by a laser printer controller to send video signals to a laser printer engine. The frame buffer allows software to have sufficient control over the dimension of the buffer and to have sufficient time to process data by allowing software to change X and Y dimensions of the buffer.

Abstract: The present invention relates to a frame buffer used by a laser printer controller to send video signals to a laser printer engine. The frame buffer allows software to have sufficient control over the dimension of the buffer and to have sufficient time to process data by setting different input/output data widths.