Abstract: A method for generating a key stream according to an embodiment includes generating r round keys that are each N-dimensional integer vectors including elements of an integer set defined based on a prime number t, based on a random bit string, an encryption counter, and a secret key that is an N-dimensional integer vector consisting of elements of the integer set , generating a first round output vector x1 by performing a modular addition operation on an initial vector and a first round key RK1 of the r round keys with the prime number t as a modulus, and generating a key stream that is an N-dimensional integer vector consisting of elements of the integer set from the first round output vector x1 by using a second to r-th round keys of the r round keys, and one or more first round functions and a second round function.

Abstract: A liquefied gas storage tank includes a corner block disposed on a corner portion, wherein the corner block includes a lower block, an upper block and an upper connecting block, the upper block includes a first inner fixing unit and a second inner fixing unit respectively provided inside a first surface and a second surface, bonded and connected to a secondary barrier, and each having a structure in which a primary inner plywood, a primary corner insulating material, and a primary outer plywood are stacked, and an inner bent portion installed at a corner spatial portion between the first inner fixing unit and the second inner fixing unit, and both side surfaces of the inner bent portion that are perpendicular to the secondary barrier each have a height reduced from a total height of each of the first and second inner fixing units.

Abstract: An apparatus for manufacturing a secondary battery includes: an index table configured to receive a secondary battery cell, the secondary battery cell including an electrode assembly, a can accommodating the electrode assembly, and an electrode tab between the electrode assembly and the can to electrically connect the electrode assembly to the can; a laser scanner configured to irradiate laser onto an outer surface of the can to weld the electrode tab to the can; and a controller configured to variably control the laser scanner according to an operation of the index table.

Abstract: The liquefied gas storage tank includes a primary barrier, a primary insulation wall, a secondary barrier, and a secondary insulation wall. In a state where unit elements are arranged adjacent to each other, each of the unit elements being formed by stacking the secondary insulation wall, the secondary barrier, and a fixed insulation wall which is a part of the primary insulation wall, the primary insulation wall may comprise: a connection insulation wall provided in the space between the adjacent fixed insulation walls; first slits formed between the fixed insulation walls and the connection insulation wall when the connection insulation wall is inserted and installed between the adjacent fixed insulation walls; a plurality of second slits formed in a lengthwise direction and a widthwise direction of the fixed insulation walls; and a first insulating filler material for filling the first slits.

Abstract: This invention relates to a method for producing chlorine in a high yield through a hydrogen chloride oxidation reaction and more specifically, this invention is characterized in that chlorine is produced in a high yield by subjecting hydrogen chloride to an oxidation reaction in a mixed gas containing carbon oxide.

Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.

Abstract: A memory device, including a memory cell array including a plurality of memory cell rows; a monitoring cell array configured to detect a victim memory cell row of the plurality of memory cell rows, and to generate bit data; a bit data decoder configured to: receive the bit data, and based on the bit data, generate a victim memory address including address information about the victim memory cell row; and a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address

Abstract: A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

Abstract: A memory device including a memory bank array which includes a first edge memory block, a second edge memory block, and a plurality of memory blocks placed between the first edge memory block and the second edge memory block; a plurality of sense amplifiers between the plurality of memory blocks, and that connect a first bit line of a memory block on one side of each of the plurality of sense amplifiers and a first complementary bit line of a memory block on an other side of each of the plurality of sense amplifiers; a first edge sense amplifier connected to a second bit line and a second complementary bit line of the first edge memory block; and a second edge sense amplifier connected to a third bit line and a third complementary bit line of the second edge memory block.

Abstract: According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.

Abstract: Disclosed is an air conditioner including a first frame including a through hole, a second frame rotatably coupleable to the first frame, the second frame including a burring portion at least a portion of which is insertable into the through-hole in a first direction, where while the burring portion is inserted into the through-hole of the first frame, the burring portion protrudes in the first direction, and a burring hole formed by the burring portion, and a fastening member insertable into the burring hole in a second direction opposite to the first direction and configured to function as a rotary shaft of the second frame, where while the fastening member is inserted into the burring hole, the fastening member protrudes in the second direction.

Abstract: Disclosed is a method for accessing memory cells arranged in rows and columns. The method includes activating a specific row of the rows of the memory cells, and flipping data bits stored in memory cells of the specific row in response to determining that concentrated activation occurs at the specific row.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips that are stacked, wherein each of the memory chips includes a memory cell array, which includes a plurality of memory cell rows, a chip identifier generator configured to generate a chip identifier signal indicating a chip identifier of each of the memory chips, a refresh counter configured to generate a target row address for refreshing the memory cell rows in response to a refresh command, and a target row address generator, which receives the chip identifier signal and the target row address and outputs one of the target row address and an inverted target row address, obtained by inverting the target row address, as a refresh row address based on the chip identifier signal, and performs a refresh operation on a memory cell row corresponding to the refresh row address.

Abstract: Disclosed is an air conditioner including a first frame including a through hole, a second frame rotatably coupleable to the first frame, the second frame including a burring portion at least a portion of which is insertable into the through-hole in a first direction, where while the burring portion is inserted into the through-hole of the first frame, the burring portion protrudes in the first direction, and a burring hole formed by the burring portion, and a fastening member insertable into the burring hole in a second direction opposite to the first direction and configured to function as a rotary shaft of the second frame, where while the fastening member is inserted into the burring hole, the fastening member protrudes in the second direction.

Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.

Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.