Abstract: The invention relates to word line selection logic circuits for a semiconductor memory device composed of a plurality of memory blocks. Word line selection logic circuits are composed of groups of word line blocks, and semiconductors for switches operated by an output signal from a block selection decoder to activate a selected word line block. The switches are assigned to each block, and one of the word lines within the memory blocks is selected by supplying the activated word line block with an output signal from a row decoder which ensures improvement in access time and high density.