Patents by Inventor Seong Jun Ahn

Seong Jun Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230070603
    Abstract: Disclosed are a polyamide resin composition and a molded article manufactured using the same. The molded article may have excellent mechanical strength, deformation resistance and light resistance, and may be suitable for use without coating. The polyamide resin composition includes a polyamide resin, an auxiliary resin (e.g., an acrylonitrile-butadiene-styrene copolymer), a filler (e.g., glass fibers and glass beads), and a compatibilizer (e.g., copolymer including maleimide).
    Type: Application
    Filed: August 8, 2022
    Publication date: March 9, 2023
    Inventors: Seul Yi, Boo Youn An, Dae Sik Kim, Kyeong Hoon Jang, In Soo Han, Jin Gi Ahn, Seong Hyun Myung, Seong Jun Yu, Jung Hyun Yoo, Ki Bong Jung
  • Patent number: 11600676
    Abstract: A display device includes a display part including a plurality of pixels arranged on a substrate, a plurality of dams in a first peripheral part adjacent to the display part, the plurality of dams being extended in a first direction of the first peripheral part and arranged in a second direction crossing the first direction, each of the plurality of dams including at least one selected from a first organic insulating layer and a second organic insulating layer, and a blocking part disposed between the plurality of dams and corresponding to a removed portion of the first and second organic insulating layers.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Ho Bang, Nayun Kwak, Eunhye Kim, Sae bom Ahn, Seong Ryoung Lee, Sanghyun Jun, Wonsuk Choi
  • Publication number: 20230048824
    Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.
    Type: Application
    Filed: November 30, 2021
    Publication date: February 16, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Seong Jun PARK, Jong Min CHO, Sung Bum PARK, Kee Sik AHN
  • Patent number: 11538541
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: December 27, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11532075
    Abstract: A display apparatus is provided. The display apparatus includes an input interface, a first storage, a display, and a processor. Pixel values corresponding to a predetermined number of lines in an image input through the input interface are stored in the first storage. The processor acquires a first patch of a predetermined size by sampling a number of pixel values located in an outer region of a matrix centering about a specific pixel value from among the pixel values stored in the first storage, acquires a high-frequency component for the specific pixel value based on the acquired first patch, and processes the input image based on the high-frequency component. The display displays the processed image.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-jun Lim, Seok-bong Yoo, Tae-gyoung Ahn, Young-su Moon, Seong-hoon Choi
  • Patent number: 11464770
    Abstract: Provided is a method for treating or preventing cancer, containing, as an active ingredient, a compound having a specific chemical structure and an activity of inhibiting the formation of a c-Myc/Max/DNA complex, or a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: October 11, 2022
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Kyung Chae Jeong, Hwan Jung Lim, Seong Jun Park, Ho Kyung Seo, Kyung Ohk Ahn, Sang Jin Lee, Eun Sook Lee
  • Publication number: 20220306718
    Abstract: The present invention relates to a transmembrane domain derived from human LRRC24 protein. More specifically, the present invention relates to a transmembrane domain derived from the human LRRC24 protein (LRRC24P transmembrane domain) or a cell-penetrating peptide, and an intracellular delivery system comprising same. The transmembrane domain derived from the human LRRC24 protein of the present invention can be used to deliver cargo materials such as compounds, biomolecules, and various polymer materials into cells. Since the LRRC24P transmembrane domain of the present invention exhibits higher cell penetration efficiency compared to conventional cell-penetrating peptides and is derived from human proteins, thus avoiding side effects and immune responses caused by peptides derived from foreign proteins, it can be usefully used as an effective intracellular delivery method for compounds, biomolecules, and various polymer materials applied to the human body.
    Type: Application
    Filed: December 16, 2019
    Publication date: September 29, 2022
    Inventors: Seong Jun KIM, Kyun Do KIM, In Su HWANG, Keunbon KU, Chonsaeng KIM, Bum Tae KIM, Dae Gyun AHN, Hae Soo KIM, Young Chan KWON
  • Patent number: 10409715
    Abstract: In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hwan Bae, Chan-Ik Park, Hyun-Jin Choi, Seong-Jun Ahn, In-Hwan Doh
  • Patent number: 10048892
    Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-kwon Moon, Jong-youl Lee, Seong-jun Ahn, Hee-won Lee
  • Publication number: 20180052768
    Abstract: In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.
    Type: Application
    Filed: April 10, 2017
    Publication date: February 22, 2018
    Inventors: SUNG-HWAN BAE, CHAN-IK PARK, HYUN-JIN CHOI, SEONG-JUN AHN, IN-HWAN DOH
  • Publication number: 20170351459
    Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.
    Type: Application
    Filed: February 10, 2017
    Publication date: December 7, 2017
    Inventors: Sang-kwon MOON, Jong-youl Lee, Seong-jun Ahn, Hee-won Lee
  • Patent number: 9798498
    Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Jin Cho, Seong Nam Kwon, Hyun Seok Kim, Jae Geun Park, Seong Jun Ahn, Mi Hyang Lee
  • Publication number: 20160005480
    Abstract: A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level.
    Type: Application
    Filed: July 1, 2015
    Publication date: January 7, 2016
    Inventors: DONG-GUN KIM, SEONG-JUN AHN, HYUN-SEOK KIM, YANG-WOO ROH, SUNG-HWAN BAE, JONG-YOUL LEE, SE-JEONG JANG
  • Publication number: 20150363338
    Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.
    Type: Application
    Filed: April 21, 2015
    Publication date: December 17, 2015
    Inventors: Young Jin CHO, Seong Nam KWON, Hyun Seok KIM, Jae Geun PARK, Seong Jun AHN, Mi Hyang LEE
  • Patent number: 8935460
    Abstract: A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-ho Park, Seong-jun Ahn, Min-cheol Kwon
  • Patent number: 8639891
    Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi Kyeong Kang, Dong Jun Shin, Shin-Ho Choi, Seong Jun Ahn, Min Cheol Kwon, Shine Kim, Sun-Mi Yoo
  • Patent number: 8595412
    Abstract: A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Cheol Kwon, Dong Jun Shin, Seong Jun Ahn, Shin-Ho Choi, Shine Kim, Sun-Mi Yoo, Mi Kyeong Kang
  • Publication number: 20130305008
    Abstract: A method of controlling operation timing of memory devices included in a storage apparatus and a memory system including the method. The method includes adjusting operation timing such that a number of memory devices that simultaneously perform operations is below a reference value according to a host request, and issuing operations according to the adjusted operation timing and transferring the issued operations to the memory devices.
    Type: Application
    Filed: March 15, 2013
    Publication date: November 14, 2013
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jea-young Kwon, Shine Kim, Seong-jun Ahn, Woo-seok Chang, Da-woon Jung
  • Publication number: 20130024607
    Abstract: A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 24, 2013
    Inventors: Young-ho Park, Seong-jun Ahn, Min-cheol Kwon
  • Patent number: 7990765
    Abstract: A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device includes setting first through nth LSB page groups (n being a natural number that is larger than 2) comprising at least two LSB pages from among the LSB pages included in the MLC flash memory, programming the first through xth LSB pages (x is a natural number that is larger than 2) included in an ith LSB page group (i is a natural number that is smaller than n), generating and storing an ith LSB parity page for the first through xth LSB pages, programming first through xth MSB pages which correspond to one LSB page from among the first through xth LSB pages, and recovering a jth LSB page, which are paired with a jth MSB page, using the ith LSB parity page corresponding to the ith LSB page group, when a power supply to the MLC flash memory is stopped during the programming of the jth MSB page (j is a natural number that is smaller than x).
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-min Park, Seong-jun Ahn