Abstract: The present disclosure relates to an electronic device, and more specifically, to an electronic device including a printed circuit board including a heat-generating element arranged on one surface thereof, and a heat transfer coin provided such that one surface of the heat transfer coin comes into contact with a portion of the other surface of the printed circuit board, opposite to the heat-generating element, so as to dissipate heat generated from the heat-generating element. Accordingly, the present disclosure provides an advantage of improving heat dissipation performance without increasing the thickness of the printed circuit board.

Abstract: A communication apparatus is provided to include an apparatus enclosure that includes a substrate seating surface and at least one or more connection grooves formed on the substrate seating surface, a first printed circuit board disposed on the substrate seating surface, a second printed circuit board disposed on the substrate seating surface on one side of the first printed circuit board, and at least one or more connectors disposed within the connection groove and configured to electrically connect the first printed circuit board and the second printed circuit board.

Abstract: The present invention relates to a signal shielding apparatus and an antenna apparatus including same, and in particular, comprises a shield cover which is stacked and disposed on a printed board assembly (hereinafter, abbreviated to “PBA”), in which a plurality of signal-related components are mounted on one side thereof to prevent leakage of a signal from the plurality of signal-related components, wherein a grooved shield cover seating groove is formed in one surface of the PBA, and an insertion end insertably seated in the shield cover seating groove is integrally formed in the other surface from among one surface and the other surface of the shield cover, the other surface facing the one surface of the PBA, thereby providing advantages in that an increase in the manufacturing cost may be prevented, EMI shielding may be facilitated, and heat dissipation performance may be significantly improved.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.

Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.

Abstract: In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.

Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.

Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.

Abstract: A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level.

Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.

Abstract: A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.

Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.

Abstract: A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group.

Abstract: A method of controlling operation timing of memory devices included in a storage apparatus and a memory system including the method. The method includes adjusting operation timing such that a number of memory devices that simultaneously perform operations is below a reference value according to a host request, and issuing operations according to the adjusted operation timing and transferring the issued operations to the memory devices.

Abstract: A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.

Abstract: A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device includes setting first through nth LSB page groups (n being a natural number that is larger than 2) comprising at least two LSB pages from among the LSB pages included in the MLC flash memory, programming the first through xth LSB pages (x is a natural number that is larger than 2) included in an ith LSB page group (i is a natural number that is smaller than n), generating and storing an ith LSB parity page for the first through xth LSB pages, programming first through xth MSB pages which correspond to one LSB page from among the first through xth LSB pages, and recovering a jth LSB page, which are paired with a jth MSB page, using the ith LSB parity page corresponding to the ith LSB page group, when a power supply to the MLC flash memory is stopped during the programming of the jth MSB page (j is a natural number that is smaller than x).

Abstract: A method of prefetching data in a hard disk drive includes searching for a logic block address (LBA) of data requested by an external apparatus in a history of a non-volatile cache of the hard disk drive, and if the LBA of the data is stored in the history, storing data recorded in a LBA stored after the LBA of the data requested by the external apparatus from among LBAs stored in the history in a buffer of the hard disk drive.

Abstract: A data storage device capable of improving reading and writing performance includes at least one memory chip comprising a control unit and a plurality of blocks for storing data, and communicating with a host through a channel; and memory storing data output from the at least one memory chip. The control unit may sequentially read data having continuous logic addresses and discontinuous physical addresses from the plurality of blocks and store the data in the memory to have continuous physical addresses.

Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.