Patents by Inventor Seong Jun Ahn
Seong Jun Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250124993Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells; and a sense amplifier configured to read data from the plurality of memory cells and output the read data. The sense amplifier includes a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.Type: ApplicationFiled: December 19, 2024Publication date: April 17, 2025Applicant: SK keyfoundry Inc.Inventors: Seong Jun PARK, Sung Bum PARK, Kee Sik AHN
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Patent number: 12260915Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.Type: GrantFiled: March 14, 2022Date of Patent: March 25, 2025Assignee: SK keyfoundry Inc.Inventors: Seong Jun Park, Jong Min Cho, Sung Bum Park, Kee Sik Ahn
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Patent number: 12224025Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.Type: GrantFiled: November 6, 2023Date of Patent: February 11, 2025Assignee: SK Keyfoundry Inc.Inventors: Seong Jun Park, Sung Bum Park, Kee Sik Ahn
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Patent number: 12202876Abstract: The present invention relates to a transmembrane domain derived from human LRRC24 protein. More specifically, the present invention relates to a transmembrane domain derived from the human LRRC24 protein (LRRC24P transmembrane domain) or a cell-penetrating peptide, and an intracellular delivery system comprising same. The transmembrane domain derived from the human LRRC24 protein of the present invention can be used to deliver cargo materials such as compounds, biomolecules, and various polymer materials into cells. Since the LRRC24P transmembrane domain of the present invention exhibits higher cell penetration efficiency compared to conventional cell-penetrating peptides and is derived from human proteins, thus avoiding side effects and immune responses caused by peptides derived from foreign proteins, it can be usefully used as an effective intracellular delivery method for compounds, biomolecules, and various polymer materials applied to the human body.Type: GrantFiled: December 16, 2019Date of Patent: January 21, 2025Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Seong Jun Kim, Kyun Do Kim, In Su Hwang, Keunbon Ku, Chonsaeng Kim, Bum Tae Kim, Dae Gyun Ahn, Hae Soo Kim, Young Chan Kwon
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Patent number: 10409715Abstract: In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.Type: GrantFiled: April 10, 2017Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Hwan Bae, Chan-Ik Park, Hyun-Jin Choi, Seong-Jun Ahn, In-Hwan Doh
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Patent number: 10048892Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.Type: GrantFiled: February 10, 2017Date of Patent: August 14, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-kwon Moon, Jong-youl Lee, Seong-jun Ahn, Hee-won Lee
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Publication number: 20180052768Abstract: In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.Type: ApplicationFiled: April 10, 2017Publication date: February 22, 2018Inventors: SUNG-HWAN BAE, CHAN-IK PARK, HYUN-JIN CHOI, SEONG-JUN AHN, IN-HWAN DOH
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Publication number: 20170351459Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.Type: ApplicationFiled: February 10, 2017Publication date: December 7, 2017Inventors: Sang-kwon MOON, Jong-youl Lee, Seong-jun Ahn, Hee-won Lee
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Patent number: 9798498Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.Type: GrantFiled: April 21, 2015Date of Patent: October 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Seong Nam Kwon, Hyun Seok Kim, Jae Geun Park, Seong Jun Ahn, Mi Hyang Lee
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Publication number: 20160005480Abstract: A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level.Type: ApplicationFiled: July 1, 2015Publication date: January 7, 2016Inventors: DONG-GUN KIM, SEONG-JUN AHN, HYUN-SEOK KIM, YANG-WOO ROH, SUNG-HWAN BAE, JONG-YOUL LEE, SE-JEONG JANG
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Publication number: 20150363338Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.Type: ApplicationFiled: April 21, 2015Publication date: December 17, 2015Inventors: Young Jin CHO, Seong Nam KWON, Hyun Seok KIM, Jae Geun PARK, Seong Jun AHN, Mi Hyang LEE
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Patent number: 8935460Abstract: A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.Type: GrantFiled: July 12, 2012Date of Patent: January 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ho Park, Seong-jun Ahn, Min-cheol Kwon
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Patent number: 8639891Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.Type: GrantFiled: March 24, 2010Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Mi Kyeong Kang, Dong Jun Shin, Shin-Ho Choi, Seong Jun Ahn, Min Cheol Kwon, Shine Kim, Sun-Mi Yoo
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Patent number: 8595412Abstract: A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group.Type: GrantFiled: April 6, 2010Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Min Cheol Kwon, Dong Jun Shin, Seong Jun Ahn, Shin-Ho Choi, Shine Kim, Sun-Mi Yoo, Mi Kyeong Kang
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Publication number: 20130305008Abstract: A method of controlling operation timing of memory devices included in a storage apparatus and a memory system including the method. The method includes adjusting operation timing such that a number of memory devices that simultaneously perform operations is below a reference value according to a host request, and issuing operations according to the adjusted operation timing and transferring the issued operations to the memory devices.Type: ApplicationFiled: March 15, 2013Publication date: November 14, 2013Applicant: Samsung Electronics Co., LtdInventors: Jea-young Kwon, Shine Kim, Seong-jun Ahn, Woo-seok Chang, Da-woon Jung
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Publication number: 20130024607Abstract: A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block.Type: ApplicationFiled: July 12, 2012Publication date: January 24, 2013Inventors: Young-ho Park, Seong-jun Ahn, Min-cheol Kwon
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Patent number: 7990765Abstract: A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device includes setting first through nth LSB page groups (n being a natural number that is larger than 2) comprising at least two LSB pages from among the LSB pages included in the MLC flash memory, programming the first through xth LSB pages (x is a natural number that is larger than 2) included in an ith LSB page group (i is a natural number that is smaller than n), generating and storing an ith LSB parity page for the first through xth LSB pages, programming first through xth MSB pages which correspond to one LSB page from among the first through xth LSB pages, and recovering a jth LSB page, which are paired with a jth MSB page, using the ith LSB parity page corresponding to the ith LSB page group, when a power supply to the MLC flash memory is stopped during the programming of the jth MSB page (j is a natural number that is smaller than x).Type: GrantFiled: September 10, 2009Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-min Park, Seong-jun Ahn
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Patent number: 7979631Abstract: A method of prefetching data in a hard disk drive includes searching for a logic block address (LBA) of data requested by an external apparatus in a history of a non-volatile cache of the hard disk drive, and if the LBA of the data is stored in the history, storing data recorded in a LBA stored after the LBA of the data requested by the external apparatus from among LBAs stored in the history in a buffer of the hard disk drive.Type: GrantFiled: July 17, 2008Date of Patent: July 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-jun Ahn, Hyung-gyu Lee, Jung-hwan Kim, Young-bong Kim, Sine Kim, Young-il Seo, Chan-ho Park
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Publication number: 20100306491Abstract: A data storage device capable of improving reading and writing performance includes at least one memory chip comprising a control unit and a plurality of blocks for storing data, and communicating with a host through a channel; and memory storing data output from the at least one memory chip. The control unit may sequentially read data having continuous logic addresses and discontinuous physical addresses from the plurality of blocks and store the data in the memory to have continuous physical addresses.Type: ApplicationFiled: March 16, 2010Publication date: December 2, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-mi Yoo, Min-cheol Kwon, Seong-jun Ahn, Shine Kim, Mi-kyeong Kang
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Publication number: 20100274976Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.Type: ApplicationFiled: March 24, 2010Publication date: October 28, 2010Inventors: Mi Kyeong Kang, Dong Jun Shin, Shin-Ho Choi, Seong Jun Ahn, Min Cheol Kwon, Shine Kim, Sun-Mi Yoo