Abstract: Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.

Abstract: Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the memory block may be received and temporarily stored. Then, the rows selected by the temporarily stored addresses may be simultaneously activated, and at least some of the memory cells in the activated rows are simultaneously programmed. Corresponding non-volatile memory devices are also provided.

Abstract: A multi-chip system and a boot code fetch method include a nonvolatile memory chip storing a volatile memory chip, and a boot code, and a host fetching the boot code. The boot code is transferred to the volatile memory chip before the host fetches the boot code in the nonvolatile memory chip, and the boot code is fetched in the volatile memory chip. Therefore, a bootRAM of the conventional nonvolatile memory chip may be removed, so that an area of the nonvolatile memory chip can be reduced.

Abstract: In a NOR-NAND flash memory device, data bits may be alternately selected from first and second mats. A selected wordline in a mat may be kept active until completing a read operation for data bits of more than one memory cells coupled to the selected wordline.

Abstract: Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.

Abstract: An MMC form-factor flash memory device can include a non-volatile memory cell array and a multimedia card interface circuit that is configured to interface with an external host system using a multimedia card communication protocol. A peripheral circuit is configured to control read/program/erase operations of the non-volatile memory cell array under the control of the multimedia card interface circuit, wherein the non-volatile memory cell array, the multimedia card interface circuit, and the peripheral circuit are on a single integrated circuit chip. Related methods of operating are also disclosed.

Abstract: Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

Abstract: A flash memory device for performing a bad block management and a method of performing bad block management are implemented in hardware level. During a booting procedure of a flash memory device, a bad block-mapping table stored in a predetermined block of memory cell array unit or other nonvolatile memory is stored in a bad block mapping register via a bad block-mapping table loader. An address selector receives a logical address from an external device and compares the logical address with a bad block address stored in the bad block mapping register. A bad block-state controller determines a count number of a re-mapping mark and outputs a re-mapping mark flag to the address selector. The address selector selects a logical address or a bad block address received from the bad block mapping register as a physical address and outputs the physical address to the memory cell array unit.

Abstract: Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the memory block may be received and temporarily stored. Then, the rows selected by the temporarily stored addresses may be simultaneously activated, and at least some of the memory cells in the activated rows are simultaneously programmed. Corresponding non-volatile memory devices are also provided.

Abstract: Methods for automatically refreshing a plurality of memory cells in a volatile memory device are provided in which an auto-refresh mode of the volatile memory device is activated in response to an auto-refresh mode activation command. Thereafter, an auto-refresh operation may be performed on the plurality of memory cells in response to an auto-refresh command. Related dynamic random access memory devices, memory systems and logic embedded memories are also provided.

Abstract: In a self-refresh mode, alternative refresh commands such as auto-refresh and row active commands are applied to a volatile memory device in response to stored refresh and address information to implement different refresh times for memory cells having different refresh characteristics.

Abstract: Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the memory block may be received and temporarily stored. Then, the rows selected by the temporarily stored addresses may be simultaneously activated, and at least some of the memory cells in the activated rows are simultaneously programmed. Corresponding non-volatile memory devices are also provided.

Abstract: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.

Abstract: In a NOR-NAND flash memory device, data bits may be alternately selected from first and second mats. A selected wordline in a mat may be kept active until completing a read operation for data bits of more than one memory cells coupled to the selected wordline.

Abstract: An MMC form-factor flash memory device can include a non-volatile memory cell array and a multimedia card interface circuit that is configured to interface with an external host system using a multimedia card communication protocol. A peripheral circuit is configured to control read/program/erase operations of the non-volatile memory cell array under the control of the multimedia card interface circuit, wherein the non-volatile memory cell array, the multimedia card interface circuit, and the peripheral circuit are on a single integrated circuit chip. Related methods of operating are also disclosed.

Abstract: Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

Abstract: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.

Abstract: Methods are provided to program a memory device having a plurality of memory blocks. A first address for selecting a row of each of the memory blocks is generated according to a multi-page program operation. A second address for selecting a memory block is received and latched, which is repeated until second addresses of memory blocks to be selected are all received and latched. Memory blocks are selected by the latched second addresses, and then the same rows of the respective selected memory blocks are simultaneously activated according to the first address. Related memory devices also are described.

Abstract: In a self-refresh mode, alternative refresh commands such as auto-refresh and row active commands are applied to a volatile memory device in response to stored refresh and address information to implement different refresh times for memory cells having different refresh characteristics.

Abstract: Methods for automatically refreshing a plurality of memory cells in a volatile memory device are provided in which an auto-refresh mode of the volatile memory device is activated in response to an auto-refresh mode activation command. Thereafter, an auto-refresh operation may be performed on the plurality of memory cells in response to an auto-refresh command. Related dynamic random access memory devices, memory systems and logic embedded memories are also provided.