Abstract: Provided are a method for generating a summary and a system therefor. The method according to some embodiments may include calculating a likelihood loss for a summary model using a first text sample and a first summary sentence corresponding to the first text sample, calculating an unlikelihood loss for the summary model using a second text sample and the first summary sentence, the second text sample being a negative sample generated from the first text sample, and updating the summary model based on the likelihood loss and the unlikelihood loss.

Abstract: A method for manufacturing a LiDAR device is proposed. The method may include providing a LiDAR module including a laser emitting module and a laser detecting module to a target region. The method may also include adjusting, on the basis of first detecting data obtained from the laser detecting module, a relative position of a detecting optic module with respect to the laser detecting module. The method may further include adjusting, on the basis of image data obtained from at least one image sensor, a relative position of an emitting optic module with respect to the laser emitting module.

Abstract: A battery pack is advantageous for effective control and maintenance of thermal events. A battery pack according to one aspect of the present disclosure may include a battery module having one or more battery cells; a fire extinguishing tank holding a fire extinguishing liquid, disposed on top of the battery module and having a through hole formed therein; and a cover member installed in the through hole of the fire extinguishing tank and configured to open or close the through hole according to a change in internal pressure of the fire extinguishing tank.

Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.

Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.

Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.

Abstract: Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.

Abstract: Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.

Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

Abstract: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process.

Abstract: A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode.

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Abstract: A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.

Abstract: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process.

Abstract: A method of manufacturing a stack-type semiconductor device, in which a first substrate and a second substrate are prepared so that the first substrate has a surface layer and the second substrate has an insulation layer. The first substrate and the second substrate are attached to each other to allow the surface layer to make contact with the insulation layer. The first substrate is partially separated from the second substrate to allow the surface layer to remain on a central portion of the second substrate. A sacrificial layer pattern is then formed on an edge portion of the second substrate having the surface layer. The sacrificial layer pattern and the surface layer are planarized. Thus, the sacrificial layer pattern may reduce damage to the edge portion of the second substrate so that the second substrate may have an improved flatness.

Abstract: In a method of recycling a substrate having an edge portion on which a stepped portion is formed, the substrate is chemically mechanically polished using a first slurry composition including fumed silica to remove the stepped portion. The substrate is then chemically mechanically polished using a second slurry composition including colloidal silica to improve the surface roughness of the substrate. The substrate having the edge region on which the stepped portion is formed may include a donor substrate used for manufacturing a silicon-on-insulator (SOI) substrate.

Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.