Patents by Inventor Seong-Kyu Yun

Seong-Kyu Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9793133
    Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
  • Publication number: 20150214289
    Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
    Type: Application
    Filed: October 8, 2014
    Publication date: July 30, 2015
    Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
  • Patent number: 8470663
    Abstract: Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Kyu Yun, Jae-Seok Kim
  • Publication number: 20110256676
    Abstract: Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.
    Type: Application
    Filed: March 15, 2011
    Publication date: October 20, 2011
    Inventors: Seong-Kyu Yun, Jae-Seok Kim
  • Patent number: 8008172
    Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Seong-Kyu Yun, Suk-Hun Choi, Sang-Yeob Han
  • Patent number: 7932163
    Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Dae-Lok Bae, Seong-Kyu Yun, Suk-Hun Choi
  • Patent number: 7846801
    Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-jun Kim, Seong-kyu Yun, Chang-ki Hong, Bo-un Yoon, Jong-won Lee, Ho-young Kim
  • Patent number: 7678625
    Abstract: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: March 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Seong-Kyu Yun, Suk-Hun Choi, Sang-Yeob Han
  • Publication number: 20080247219
    Abstract: A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 9, 2008
    Inventors: Suk-Hun Choi, In-Gyu Baek, Seong-Kyu Yun, Jong-Heun Lim, Chagn-Ki Hong, Bo-Un Yoon
  • Publication number: 20080200009
    Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 21, 2008
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Dae-Lok Bae, Seong-Kyu Yun, Suk-Hun Choi
  • Publication number: 20080200007
    Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 21, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Seong-Kyu Yun, Suk-Hun Choi, Sang-Yeob Han
  • Publication number: 20080164503
    Abstract: A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Inventors: Suk-Hun Choi, Chang-Ki Hong, Jung-Hyeon Kim, Jun-Young Lee, Jong-Heun Lim, Seong-Kyu Yun
  • Publication number: 20080160726
    Abstract: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 3, 2008
    Inventors: Jong Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Seong-Kyu Yun, Suk-Hun Choi, Sang-Yeob Han
  • Publication number: 20080138960
    Abstract: A method of manufacturing a stack-type semiconductor device, in which a first substrate and a second substrate are prepared so that the first substrate has a surface layer and the second substrate has an insulation layer. The first substrate and the second substrate are attached to each other to allow the surface layer to make contact with the insulation layer. The first substrate is partially separated from the second substrate to allow the surface layer to remain on a central portion of the second substrate. A sacrificial layer pattern is then formed on an edge portion of the second substrate having the surface layer. The sacrificial layer pattern and the surface layer are planarized. Thus, the sacrificial layer pattern may reduce damage to the edge portion of the second substrate so that the second substrate may have an improved flatness.
    Type: Application
    Filed: November 8, 2007
    Publication date: June 12, 2008
    Inventors: Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Young-Ho Koh, Seong-Kyu Yun, Jong-Heun Lim
  • Publication number: 20080124930
    Abstract: In a method of recycling a substrate having an edge portion on which a stepped portion is formed, the substrate is chemically mechanically polished using a first slurry composition including fumed silica to remove the stepped portion. The substrate is then chemically mechanically polished using a second slurry composition including colloidal silica to improve the surface roughness of the substrate. The substrate having the edge region on which the stepped portion is formed may include a donor substrate used for manufacturing a silicon-on-insulator (SOI) substrate.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Inventors: Jong Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Dae-Lok Bae, Seong-Kyu Yun, Suk-Hun Choi
  • Publication number: 20080045019
    Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
    Type: Application
    Filed: August 2, 2007
    Publication date: February 21, 2008
    Inventors: Sung-jun Kim, Seong-kyu Yun, Chang-ki Hong, Bo-un Yoon, Jong-won Lee, Ho-young Kim
  • Publication number: 20060037942
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming a surface of a capacitor using the slurry. The slurry may include an abrasive, an oxidizer, and at least one pH controller to control a pH of the slurry.
    Type: Application
    Filed: June 30, 2005
    Publication date: February 23, 2006
    Inventors: Seong-Kyu Yun, Kenichi Orui, Chang-Ki Hong, Jae-Dong Lee, Sung-Jun Kim, Haruki Nojo