Abstract: An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.

Abstract: Provided herein is a composition of a polypropylene resin with improved foaming capability with improved foaming capability, such as a polypropylene comprising a foaming agent master batch and a highly flowable polypropylene resin having non-controlled rheology. The resin composition exhibits excellent foaming quality and can be easily injected. The polypropylene resin with improved foaming capability comprises a mixture comprising from about 50% to about 80% by weight of a polypropylene resin having a mean molecular weight of about 45,000 g/mol to about 180,000 g/mol, from about 15% to about 30% by weight of a fiber reinforcing agent, and from about 2% to about 20% by weight of a foaming agent.

Abstract: The present invention relates to a polypeptide (repebody) selectively bound to an immunoglobulin G, a polynucleotide which encodes the repebody, a vector containing the polynucleotide, a recombinant microorganism in which the polynucleotide is introduced, a method for producing the repebody using the recombinant microorganism, and a method for immobilizing or purifying an immunoglobulin G using the repebody. The repebody according to the present invention is useful as utilized for immobilization of an immunoglobulin G, purification of an immunoglobulin G, and production of an immunosensor, since the repebody selectively bound to an immunoglobulin G.

Abstract: A semiconductor device and an operating method thereof are provided. An operating method of a semiconductor device, includes monitoring a plurality of request packets and a plurality of response packets that are being transmitted between a master device and a slave device; detecting a target request packet that matches desired identification (ID) information from among the plurality of request packets; counting the number of events of a transaction including the target request packet by using an event counter; counting the number of request packets whose corresponding response packets are yet to be detected, from among the plurality of request packets by using a Multiple Outstanding (MO) counter, determining whether an MO count value of the MO counter is valid; and if the MO count value is invalid, resetting the event counter.

Abstract: An operating method of a semiconductor device includes monitoring multiple request packets and multiple response packets that are being transmitted between a master device and a slave device. A target request packet that matches predefined identification (ID) information is detected from among the request packets. An operation of a latency counter is initiated. The operation is for measuring the latency of a communication exchange (transaction) that includes the target request packet and a target response packet that is one of the response packets that matches the predefined ID information. The target response packet is detected from among the response packets. The operation of the latency counter is terminated. A latency value of the communication exchange is acquired from the latency counter.

Abstract: An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.

Abstract: Provided are semiconductor devices. A semiconductor device includes processors performing an operation using data stored in a memory; and a memory protector dividing the memory into a first window area and a second window area. The first window area including a first fragment page, which is of a first size. The second window area including a second fragment page, which is of a second size, wherein the second size is smaller than the first size. The memory protector configured to protect the first fragment page and the second fragment page from being accessed by the processors.

Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.

Abstract: A semiconductor device includes a first processing unit configured to perform a calculation by using data stored in a memory; and a memory path controller configured to communicate with the first processing unit and control the memory for the first processing unit to perform the calculation, wherein the memory path controller includes an address region control unit configured to divide an address space of the memory to include a secure address and a non-secure address and permit the first processing unit to access the secure address or the non-secure address, and a first content firewall unit connected with the address region control unit and configured to prevent the first processing unit from writing secure contents in the non-secure address.

Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.

Abstract: The present invention relates to a polypeptide (repebody) selectively bound to an immunoglobulin G, a polynucleotide which encodes the repebody, a vector containing the polynucleotide, a recombinant microorganism in which the polynucleotide is introduced, a method for producing the repebody using the recombinant microorganism, and a method for immobilizing or purifying an immunoglobulin G using the repebody. The repebody according to the present invention is useful as utilized for immobilization of an immunoglobulin G, purification of an immunoglobulin G, and production of an immunosensor, since the repebody selectively bound to an immunoglobulin G.

Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.

Abstract: An apparatus and method for packet routing in a high-speed packet routing system. The apparatus includes an input unit and a control unit. The input unit temporarily stores an input packet and outputs the temporarily stored input packet to an output port determined by a previous router. The control unit determines an output port of a next router for the input packet.