Abstract: A semiconductor device may include a first capacitor and a second capacitor located at a different height from the first capacitor. Each of the first and second capacitors includes a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode. A selected one of the lower and upper electrodes includes a first portion having a cylindrical shape including a closed lower surface and an opened upper surface and a second portion vertically extended from the first portion of the selected one. A selected another one of the lower and upper electrodes includes a first portion having a bar shape extended into the first portion of the selected one, a second portion vertically extended from the first portion of the selected another one, and a third portion having a disc shape between the first portion and the second portion in the selected another one.

Abstract: A semiconductor device may include a first capacitor and a second capacitor located at a different height from the first capacitor. Each of the first and second capacitors includes a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode. A selected one of the lower and upper electrodes includes a first portion having a cylindrical shape and a second portion vertically extended from the first portion of the selected one. A selected another one of the lower and upper electrodes includes a first portion having a bar shape extended into the first portion of the selected one, a second portion vertically extended from the first portion of the selected another one, and a third having a cylindrical shape between the first portion and the second portion in the selected another one to surround the first portion of the selected one.

Abstract: In a method of predicting an optimal process condition model for a semiconductor fabrication process, process parameter information of a unit process in the semiconductor fabrication process may be collected. First characteristics information of objects to be processed before the unit process and second characteristic information of processed objects after the unit process may be extracted. Process global uniformity (PGU) may be calculated using the first characteristic information and the second characteristic information. A data set of the unit process may be created using the process parameter information and the PGU. A virtual process environment function of the unit process may be created using the data set. The optimal process condition model of the unit process may be created using the virtual process environment function.

Abstract: A semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.

Abstract: A method for analyzing a semiconductor device includes repeatedly etching an entire surface of a wafer at a same etch rate by a target depth to expose a next surface of the wafer. The method includes obtaining two-dimensional structure information from each repeatedly etched surface of the wafer and serially stacking the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.

Abstract: A semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.

Abstract: A method for analyzing a semiconductor device includes repeatedly etching an entire surface of a wafer at a same etch rate by a target depth to expose a next surface of the wafer. The method includes obtaining two-dimensional structure information from each repeatedly etched surface of the wafer and serially stacking the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.

Abstract: A system for analyzing a semiconductor device includes an etching module, an analyzing module, and a computing module. The etching module may repeatedly etch an entire surface of a wafer at a same etch rate to expose a next surface of the wafer at a next depth where an object to be analyzed exits. The analyzing module may obtain two-dimensional structure information from each repeatedly etched surface of the wafer. The computing module may serially stack the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.

Abstract: A system for analyzing a semiconductor device includes an etching module, an analyzing module, and a computing module. The etching module may repeatedly etch an entire surface of a wafer at a same etch rate to expose a next surface of the wafer at a next depth where an object to be analyzed exits. The analyzing module may obtain two-dimensional structure information from each repeatedly etched surface of the wafer. The computing module may serially stack the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.

Abstract: A metrology method includes obtaining a pattern reflection light reflected from an object by irradiating a first divided light, which is generated by reflecting a polarized light, to the object; obtaining a phase-controlled mirror reflection light reflected from a reflector by irradiating a second divided light, which is generated by transmitting the polarized light, to the reflector; and obtaining a pattern of the object based on an interference signal between the pattern reflection light and the mirror reflection light.

Abstract: A metrology method includes obtaining a pattern reflection light reflected from an object by irradiating a first divided light, which is generated by reflecting a polarized light, to the object; obtaining a phase-controlled mirror reflection light reflected from a reflector by irradiating a second divided light, which is generated by transmitting the polarized light, to the reflector; and obtaining a pattern of the object based on an interference signal between the pattern reflection light and the mirror reflection light.