Abstract: Provided is a method of manufacturing a capacitor of a display apparatus, the display apparatus being formed on a substrate and including a thin film transistor, which includes an active layer, a gate electrode, and source and drain electrodes, a display device connected to the thin film transistor, and the capacitor, the method including: forming an electrode layer on the substrate; forming a passivation layer on the electrode layer; patterning the passivation layer to form a first pattern including first branch patterns parallel to each other, and a second pattern including second branch patterns parallel to each other and interposed between the first branch patterns; and forming first and second electrodes by etching the electrode layer using the first and second patterns as masks.

Abstract: A display apparatus is disclosed. In one aspect the apparatus includes a touch panel, an information processor, a memory and a display panel. The touch panel generates a current touch signal including a current touch position of a touch. The information processor receives the current touch signal from the touch panel and a stored touch signal to compare the stored touch signal with the current touch signal to generate dynamic luminance information. The memory receives the current touch signal from the information processor to store the current touch signal as the stored touch signal. The display panel receives the dynamic luminance information from the information processor to display an image having different luminances in an emphasizing region corresponding to the current touch signal and the stored touch signal and a background region surrounding the emphasizing region, respectively.

Abstract: A flat panel display apparatus including a gate electrode on a substrate, a first insulating layer and a semiconductor layer sequentially stacked on the gate electrode and including a transparent conductive oxide, a capacitor first electrode extending on a plane on which the gate electrode extends, and a capacitor second electrode extending on a plane on which the semiconductor layer extends and including a material of the semiconductor layer, wherein the first insulating layer is between the capacitor second electrode and the semiconductor layer, source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode, a third insulating layer covering the source and drain electrodes, and a pixel electrode electrically connected to the source or drain electrode on the third insulating layer and being electrically connected to one of the source electrode and/or the drain electrode.

Abstract: An oxide semiconductor thin film transistor includes a gate electrode on a substrate, the gate electrode having a first area, a gate insulation layer on the gate electrode, the gate insulation layer covering the gate electrode, an active layer on the gate insulation layer, the active layer having a second area that is smaller than the first area, a source electrode on the active layer, the source electrode contacting a source region of the active layer, a drain electrode on the active layer, the drain electrode contacting a drain region of the active layer, and a passivation layer covering the active layer, the source electrode, and the drain electrode.

Abstract: An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure.

Abstract: An oxide semiconductor device may include a gate electrode formed on a substrate, and a gate insulation layer formed on the substrate to cover the gate electrode. A channel protection structure may be disposed on the gate insulation layer to expose a portion of the gate insulation layer. A source electrode may be located on a first portion of the channel protection structure. A drain electrode may be disposed on a second portion of the channel protection structure. An active pattern may be positioned on the exposed portion of the gate insulation layer, the source electrode, and the drain electrode.

Abstract: An oxide semiconductor thin film transistor includes a gate electrode on a substrate, the gate electrode having a first area, a gate insulation layer on the gate electrode, the gate insulation layer covering the gate electrode, an active layer on the gate insulation layer, the active layer having a second area that is smaller than the first area, a source electrode on the active layer, the source electrode contacting a source region of the active layer, a drain electrode on the active layer, the drain electrode contacting a drain region of the active layer, and a passivation layer covering the active layer, the source electrode, and the drain electrode.

Abstract: A flat panel display apparatus including a gate electrode on a substrate, a first insulating layer and a semiconductor layer sequentially stacked on the gate electrode and including a transparent conductive oxide, a capacitor first electrode extending on a plane on which the gate electrode extends, and a capacitor second electrode extending on a plane on which the semiconductor layer extends and including a material of the semiconductor layer, wherein the first insulating layer is between the capacitor second electrode and the semiconductor layer, source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode, a third insulating layer covering the source and drain electrodes, and a pixel electrode electrically connected to the source or drain electrode on the third insulating layer and being electrically connected to one of the source electrode and/or the drain electrode.

Abstract: The present invention relates to a method for manufacturing a SrTiO3 series varistor using grain boundary segregation, and more particularly, to a method for manufacturing a SrTiO3 series varistor by sintering a powdered composition in which acceptors such as Al and Fe are added in powdered form and then sintered under a reducing atmosphere and heat-treated them in the air to selectively form electrical conduction barriers at grain boundaries in a process for manufacturing SrTiO3 series varistor having an excellent non-linear coefficient and a breakdown voltage suitable for use.

Abstract: The present invention relates to a method for manufacturing a SrTiO3 series varistor using grain boundary segregation, and more particularly, to a method for manufacturing a SrTiO3 series varistor by sintering a powdered composition in which acceptors such as Al and Fe are added in powdered form and then sintered under a reducing atmosphere and heat-treated them in the air to selectively form electrical conduction barriers at grain boundaries in a process for manufacturing SrTiO3 series varistor having an excellent non-linear coefficient and a breakdown voltage suitable for use.